Inventor · disambiguated record
Andrew Henry Wottreng
Also filed as: WOTTRENG ANDREW H · WOTTRENG ANDREW HENRY
34 granted patents·3 pending applications·2,192 citations·filing 1980–2012
98Inventor score
Top patents by PatentIndex Score
37 records- 0198US6212544B1Altering thread priorities in a multithreaded processorIBM·Filed 1997·Granted Apr 3, 2001·537 cites·23 claims
- 0297US6567839B1Thread switch control in a multithreaded processor systemIBM·Filed 1997·Granted May 20, 2003·424 cites·34 claims
- 0395US6697935B1Method and apparatus for selecting thread switch events in a multithreaded processorIBM·Filed 1997·Granted Feb 24, 2004·273 cites·21 claims
- 0495US6076157AMethod and apparatus to force a thread switch in a multithreaded processorIBM·Filed 1997·Granted Jun 13, 2000·292 cites·17 claims
- 0589US6105051AApparatus and method to guarantee forward progress in execution of threads in a multithreaded processorIBM·Filed 1997·Granted Aug 15, 2000·148 cites·14 claims
- 0686US7814279B2Low-cost cache coherency for acceleratorsIBM·Filed 2006·Granted Oct 12, 2010·14 cites·20 claims
- 0786US5835705AMethod and system for performance per-thread monitoring in a multithreaded processorIBM·Filed 1997·Granted Nov 10, 1998·112 cites·19 claims
- 0883US6088788ABackground completion of instruction and associated fetch request in a multithread processorIBM·Filed 1996·Granted Jul 11, 2000·123 cites·19 claims
- 0982US7631131B2Priority control in resource allocation for low request rate, latency-sensitive unitsIBM·Filed 2005·Granted Dec 8, 2009·11 cites·1 claims
- 1081US6334167B1System and method for memory self-timed refresh for reduced power consumptionIBM·Filed 1998·Granted Dec 25, 2001·52 cites·11 claims
- 1176US8296547B2Loading entries into a TLB in hardware via indirect TLB entriesHEIL TIMOTHY H·Filed 2009·Granted Oct 23, 2012·8 cites·15 claims
- 1276US6880113B2Conditional hardware scan dump data captureIBM·Filed 2001·Granted Apr 12, 2005·24 cites·6 claims
- 1373US8180941B2Mechanisms for priority control in resource allocationCHEN WEN-TZER T·Filed 2009·Granted May 15, 2012·5 cites·23 claims
- 1472US7716423B2Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modesIBM·Filed 2006·Granted May 11, 2010·5 cites·10 claims
- 1570US7530068B2Method of resource allocation using an access control mechanismIBM·Filed 2003·Granted May 5, 2009·15 cites·1 claims
- 1669US5687337AMixed-endian computer systemIBM·Filed 1995·Granted Nov 11, 1997·54 cites·10 claims
- 1767US8589657B2Operating system management of address-translation-related data structures and hardware lookasidesFREY BRADLY GEORGE·Filed 2011·Granted Nov 19, 2013·2 cites·14 claims
- 1867US7552269B2Synchronizing a plurality of processorsIBM·Filed 2007·Granted Jun 23, 2009·3 cites·21 claims
- 1966US7827343B2Method and apparatus for providing accelerator support in a bus protocolIBM·Filed 2007·Granted Nov 2, 2010·3 cites·17 claims
- 2064US8327075B2Methods and apparatus for handling a cache missIRISH JOHN D·Filed 2005·Granted Dec 4, 2012·3 cites·12 claims
- 2162US7721023B2I/O address translation method for specifying a relaxed ordering for I/O accessesIBM·Filed 2005·Granted May 18, 2010·2 cites·16 claims
- 2262US5333297AMultiprocessor system having multiple classes of instructions for purposes of mutual interruptibilityIBM·Filed 1993·Granted Jul 26, 1994·37 cites·37 claims
- 2359US7472227B2Invalidating multiple address cache entriesIBM·Filed 2005·Granted Dec 30, 2008·1 cites·7 claims
- 2458US7539840B2Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2006·Granted May 26, 2009·1 cites·6 claims
- 2557US5790843ASystem for modifying microprocessor operations independently of the execution unit upon detection of preselected opcodesIBM·Filed 1996·Granted Aug 4, 1998·33 cites·32 claims
- 2656US8127082B2Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operationsMCBRIDE CHAD B·Filed 2006·Granted Feb 28, 2012·2 cites·23 claims
- 2754US7757006B2Implementing conditional packet alterations based on transmit portIBM·Filed 2008·Granted Jul 13, 2010·0 cites·8 claims
- 2853US2009187695A1Handling concurrent address translation cache misses and hits under those misses while maintaining command orderIBM·Filed 2009·Application pending·0 cites
- 2951US8645667B2Operating system management of address-translation-related data structures and hardware lookasidesFREY BRADLY GEORGE·Filed 2012·Granted Feb 4, 2014·0 cites·8 claims
- 3051US8108617B2Method to bypass cache levels in a cache coherent systemHEIL TIMOTHY H·Filed 2008·Granted Jan 31, 2012·0 cites·11 claims
- 3150US8589630B2Methods and apparatus for handling a cache missIRISH JOHN D·Filed 2012·Granted Nov 19, 2013·0 cites·20 claims
- 3248US8028118B2Using an index value located on a page table to index page attributesIBM·Filed 2007·Granted Sep 27, 2011·0 cites·19 claims
- 3348US7475161B2Implementing conditional packet alterations based on transmit portIBM·Filed 2003·Granted Jan 6, 2009·0 cites·4 claims
- 3444US8103835B2Low-cost cache coherency for acceleratorsCLARK SCOTT DOUGLAS·Filed 2010·Granted Jan 24, 2012·0 cites·19 claims
- 3543US2007180269A1I/O address translation blocking in a secure system during power-on-resetIBM·Filed 2006·Application pending·0 cites
- 3641US2007260754A1Hardware Assisted Exception for Software Miss Handling of an I/O Address Translation Cache MissIRISH JOHN D·Filed 2006·Application pending·0 cites
- 3736US4358826AApparatus for enabling byte or word addressing of storage organized on a word basisIBM·Filed 1980·Granted Nov 9, 1982·8 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →