Inventor · disambiguated record
Ramkarthik Ganesan
Also filed as: GANESAN RAMKARTHIK
10 granted patents·4 pending applications·192 citations·filing 1999–2019
89Inventor score
Top patents by PatentIndex Score
14 records- 0196US10229735B1Block management for dynamic single-level cell buffers in storage devicesINTEL CORP·Filed 2017·Granted Mar 12, 2019·57 cites·25 claims
- 0286US6297974B1Method and apparatus for reducing stress across capacitors used in integrated circuitsINTEL CORP·Filed 1999·Granted Oct 2, 2001·70 cites·24 claims
- 0379US10650886B2Block management for dynamic single-level cell buffers in storage devicesINTEL CORP·Filed 2019·Granted May 12, 2020·2 cites·18 claims
- 0478US6931498B2Status register architecture for flexible read-while-write deviceINTEL CORP·Filed 2001·Granted Aug 16, 2005·28 cites·12 claims
- 0567US7380085B2Memory adapted to provide dedicated and or shared memory to multiple processors and method thereforINTEL CORP·Filed 2001·Granted May 27, 2008·13 cites·7 claims
- 0666US10303571B2Data recovery in memory devicesINTEL CORP·Filed 2015·Granted May 28, 2019·1 cites·23 claims
- 0764US6618790B1Burst suspend and resume with computer memoryINTEL CORP·Filed 2000·Granted Sep 9, 2003·13 cites·14 claims
- 0859US7707378B2DDR flash implementation with hybrid row buffers and direct access interface to legacy flash functionsINTEL CORP·Filed 2006·Granted Apr 27, 2010·4 cites·18 claims
- 0943USRE41217EMethod and apparatus for reducing stress across capacitors used in integrated circuitsINTEL CORP·Filed 2003·Granted Apr 13, 2010·4 cites·37 claims
- 1038US8006029B2DDR flash implementation with direct register access to legacy flash functionsINTEL CORP·Filed 2006·Granted Aug 23, 2011·0 cites·15 claims
- 1137US2012191898A1Ddr flash implementation with direct register access to legacy flash functionsGANESAN RAMKARTHIK·Filed 2011·Application pending·0 cites
- 1236US2017075812A1Technologies for managing a dynamic read cache of a solid state driveINTEL CORP·Filed 2015·Application pending·0 cites
- 1334US2019034105A1Storage device having programmed cell storage density modes that are a function of storage device capacity utilizationINTEL CORP·Filed 2017·Application pending·0 cites
- 1432US2008133820A1DDR flash implementation with row buffer interface to legacy flash functionsGANESAN RAMKARTHIK·Filed 2006·Application pending·0 cites
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