Inventor · disambiguated record
Lawrence A. Clevenger
Also filed as: CLEVENGER LAWRENCE · CLEVENGER LAWRENCE A · CLEVENGER LAWRENCE ALFRED
647 granted patents·198 pending applications·5,162 citations·filing 1993–2025
99Inventor score
Top patents by PatentIndex Score
845 records- 0199US9837355B2Method for maximizing air gap in back end of the line interconnect through via landing modificationIBM·Filed 2016·Granted Dec 5, 2017·313 cites·5 claims
- 0299US7397260B2Structure and method for monitoring stress-induced degradation of conductive interconnectsIBM·Filed 2005·Granted Jul 8, 2008·169 cites·12 claims
- 0398US11538720B2Stacked transistors with different channel widthsTESSERA LLC·Filed 2020·Granted Dec 27, 2022·5 cites·17 claims
- 0498US11164817B2Multi-chip package structures with discrete redistribution layersIBM·Filed 2019·Granted Nov 2, 2021·32 cites·20 claims
- 0598US11056429B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA INC·Filed 2020·Granted Jul 6, 2021·4 cites·19 claims
- 0698US10535608B1Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrateIBM·Filed 2018·Granted Jan 14, 2020·86 cites·19 claims
- 0798US10516064B1Multiple width nanosheet devicesIBM·Filed 2018·Granted Dec 24, 2019·21 cites·20 claims
- 0898US10395986B1Fully aligned via employing selective metal depositionIBM·Filed 2018·Granted Aug 27, 2019·24 cites·19 claims
- 0998US10319629B1Skip via for metal interconnectsIBM·Filed 2018·Granted Jun 11, 2019·25 cites·20 claims
- 1098US10243020B1Structures and methods for embedded magnetic random access memory (MRAM) fabricationIBM·Filed 2017·Granted Mar 26, 2019·18 cites·13 claims
- 1198US9934970B1Self aligned pattern formation post spacer etchback in tight pitch configurationsIBM·Filed 2017·Granted Apr 3, 2018·22 cites·13 claims
- 1298US9911651B1Skip-vias bypassing a metallization level at minimum pitchIBM·Filed 2016·Granted Mar 6, 2018·26 cites·16 claims
- 1398US9761655B1Stacked planar capacitors with scaled EOTIBM·Filed 2016·Granted Sep 12, 2017·36 cites·20 claims
- 1498US9711501B1Interlayer viaIBM·Filed 2016·Granted Jul 18, 2017·34 cites·10 claims
- 1598US9660028B1Stacked transistors with different channel widthsIBM·Filed 2016·Granted May 23, 2017·93 cites·16 claims
- 1698US8241992B2Method for air gap interconnect integration using photo-patternable low k materialCLEVENGER LAWRENCE A·Filed 2010·Granted Aug 14, 2012·422 cites·18 claims
- 1798US6632741B1Self-trimming method on looped patternsIBM·Filed 2000·Granted Oct 14, 2003·341 cites·29 claims
- 1897US12218003B2Selective ILD deposition for fully aligned via with airgapADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 4, 2025·2 cites·20 claims
- 1997US11756887B2Backside floating metal for increased capacitanceIBM·Filed 2021·Granted Sep 12, 2023·5 cites·22 claims
- 2097US11152257B2Barrier-less prefilled via formationIBM·Filed 2020·Granted Oct 19, 2021·5 cites·18 claims
- 2197US11094637B2Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layersIBM·Filed 2019·Granted Aug 17, 2021·17 cites·20 claims
- 2297US10681207B1Caller identity verification based on unique multi-device signaturesIBM·Filed 2019·Granted Jun 9, 2020·35 cites·20 claims
- 2397US10431495B1Semiconductor device with local connectionIBM·Filed 2018·Granted Oct 1, 2019·18 cites·20 claims
- 2497US9991156B2Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogsIBM·Filed 2016·Granted Jun 5, 2018·15 cites·6 claims
- 2597US9966337B1Fully aligned via with integrated air gapsIBM·Filed 2017·Granted May 8, 2018·22 cites·12 claims
- 2697US9786603B1Surface nitridation in metal interconnectsIBM·Filed 2016·Granted Oct 10, 2017·14 cites·13 claims
- 2797US9741609B1Middle of line cobalt interconnectionIBM·Filed 2016·Granted Aug 22, 2017·22 cites·14 claims
- 2897US9607893B1Method of forming self-aligned metal lines and viasGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 28, 2017·22 cites·20 claims
- 2997US9553019B1Airgap protection layer for via alignmentIBM·Filed 2016·Granted Jan 24, 2017·20 cites·20 claims
- 3097US7531407B2Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating sameIBM·Filed 2006·Granted May 12, 2009·61 cites·11 claims
- 3196US10804204B2Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrateIBM·Filed 2019·Granted Oct 13, 2020·19 cites·19 claims
- 3296US9779944B1Method and structure for cut material selectionIBM·Filed 2016·Granted Oct 3, 2017·17 cites·19 claims
- 3396US9754883B1Hybrid metal interconnects with a bamboo grain microstructureIBM·Filed 2016·Granted Sep 5, 2017·14 cites·14 claims
- 3496US9735029B1Metal fill optimization for self-aligned double patterningIBM·Filed 2016·Granted Aug 15, 2017·22 cites·9 claims
- 3596US7514271B2Method of forming high density planar magnetic domain wall memoryIBM·Filed 2007·Granted Apr 7, 2009·36 cites·10 claims
- 3695US11955424B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Apr 9, 2024·1 cites·20 claims
- 3795US11894265B2Top via with damascene line and viaIBM·Filed 2021·Granted Feb 6, 2024·2 cites·19 claims
- 3895US11574864B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceTESSERA LLC·Filed 2021·Granted Feb 7, 2023·2 cites·21 claims
- 3995US11495538B2Fully aligned via for interconnectIBM·Filed 2020·Granted Nov 8, 2022·3 cites·14 claims
- 4095US11133058B1Analog computing architecture for four terminal memory devicesIBM·Filed 2020·Granted Sep 28, 2021·6 cites·20 claims
- 4195US10297750B1Wraparound top electrode line for crossbar array resistive switching deviceIBM·Filed 2017·Granted May 21, 2019·11 cites·20 claims
- 4295US10109579B2Semiconductor device including a porous dielectric layer, and method of forming the semiconductor deviceIBM·Filed 2018·Granted Oct 23, 2018·8 cites·20 claims
- 4395US10046601B2Smartwatch blackboxIBM·Filed 2017·Granted Aug 14, 2018·3 cites·20 claims
- 4495US7657995B2Method of fabricating a microelectromechanical system (MEMS) switchIBM·Filed 2007·Granted Feb 9, 2010·29 cites·4 claims
- 4595US7402532B2Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layerIBM·Filed 2006·Granted Jul 22, 2008·28 cites·1 claims
- 4695US7312529B2Structure and method for producing multiple size interconnectionsIBM·Filed 2005·Granted Dec 25, 2007·36 cites·18 claims
- 4795US6337513B1Chip packaging system and method using deposited diamond filmIBM·Filed 1999·Granted Jan 8, 2002·188 cites·17 claims
- 4894US12272648B2Semiconductor device having a backside power railIBM·Filed 2022·Granted Apr 8, 2025·2 cites·19 claims
- 4994US11276639B2Conductive lines with subtractive cutsIBM·Filed 2020·Granted Mar 15, 2022·3 cites·18 claims
- 5094US11195795B1Well-controlled edge-to-edge spacing between adjacent interconnectsIBM·Filed 2020·Granted Dec 7, 2021·3 cites·20 claims
Showing the top 50 of 845 patent records by PatentIndex Score.
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