Inventor · disambiguated record
Pavel A. Panteleev
Also filed as: PANTELEEV PAVEL · PANTELEEV PAVEL A · PANTELEEV PAVEL ANATOLYEVICH
35 granted patents·6 pending applications·85 citations·filing 2005–2023
96Inventor score
Files withLSI CORP11HUAWEI TECH CO LTD5PANTELEEV PAVEL A5FUTUREWEI TECHNOLOGIES INC4SOKOLOV ANDREY P4
Top patents by PatentIndex Score
41 records- 0194US10735138B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2018·Granted Aug 4, 2020·12 cites·20 claims
- 0284US9337866B2Apparatus for processing signals carrying modulation-encoded parity bitsLSI CORP·Filed 2013·Granted May 10, 2016·9 cites·20 claims
- 0381US11171742B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2020·Granted Nov 9, 2021·1 cites·20 claims
- 0481US8850437B2Two-pass linear complexity task schedulerSHUTKIN YURII S·Filed 2011·Granted Sep 30, 2014·8 cites·18 claims
- 0579US10567002B2Method and apparatus for encoding and decoding LDPC codesHUAWEI TECH CO LTD·Filed 2019·Granted Feb 18, 2020·3 cites·30 claims
- 0678US10594339B2Method for generating parity check matrix for low density parity check codingHUAWEI TECH CO LTD·Filed 2018·Granted Mar 17, 2020·4 cites·34 claims
- 0777US9331716B2Systems and methods for area efficient data encodingLSI CORP·Filed 2014·Granted May 3, 2016·6 cites·20 claims
- 0875US11265014B2Method and apparatus for encoding and decoding LDPC codesHUAWEI TECH CO LTD·Filed 2020·Granted Mar 1, 2022·1 cites·20 claims
- 0974US8397143B2BCH or reed-solomon decoder with syndrome modificationNEZNANOV ILYA V·Filed 2009·Granted Mar 12, 2013·10 cites·20 claims
- 1071US11664928B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 1169US7380223B2Method and system for converting netlist of integrated circuit between librariesLSI CORP·Filed 2005·Granted May 27, 2008·4 cites·20 claims
- 1265US8176397B2Variable redundancy reed-solomon encoderPANTELEEV PAVEL·Filed 2008·Granted May 8, 2012·7 cites·14 claims
- 1364US8656206B2Timer manager architecture based on binary heapGASANOV ELYAR E·Filed 2011·Granted Feb 18, 2014·2 cites·22 claims
- 1463US10862626B2Multi-label offset lifting methodFUTUREWEI TECHNOLOGIES INC·Filed 2019·Granted Dec 8, 2020·0 cites·25 claims
- 1561US8365054B2Soft reed-solomon decoder based on error-and-erasure reed-solomon decoderLSI CORP·Filed 2009·Granted Jan 29, 2013·4 cites·20 claims
- 1657US9553612B2Decoding based on randomized hard decisionsSEAGATE TECHNOLOGY LLC·Filed 2015·Granted Jan 24, 2017·1 cites·20 claims
- 1757US8539009B2Parallel true random number generator architectureALISEYCHIK PAVEL A·Filed 2008·Granted Sep 17, 2013·2 cites·21 claims
- 1852US2023419145A1Processor and method for performing tensor network contraction in quantum simulatorHUAWEI TECH CO LTD·Filed 2023·Application pending·0 cites
- 1951US8286060B2Scheme for erasure locator polynomial calculation in error-and-erasure decoderPANTELEEV PAVEL A·Filed 2008·Granted Oct 9, 2012·2 cites·18 claims
- 2051US7823050B2Low area architecture in BCH decoderLSICorporation·Filed 2006·Granted Oct 26, 2010·3 cites·1 claims
- 2150US8621329B2Reconfigurable BCH decoderPANTELEEV PAVEL A·Filed 2011·Granted Dec 31, 2013·1 cites·20 claims
- 2250US8181096B2Configurable Reed-Solomon decoder based on modified Forney syndromesANDREEV ALEXANDER·Filed 2007·Granted May 15, 2012·2 cites·20 claims
- 2349US8527851B2System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errorsANDREEV ALEXANDER E·Filed 2008·Granted Sep 3, 2013·2 cites·12 claims
- 2446US8209589B2Reed-solomon decoder with a variable number of correctable errorsANDREEV ALEXANDRE·Filed 2008·Granted Jun 26, 2012·1 cites·18 claims
- 2546US7404166B2Method and system for mapping netlist of integrated circuit to designLSI CORP·Filed 2005·Granted Jul 22, 2008·0 cites·17 claims
- 2644US2014223267A1Radix-4 viterbi forward error correction decodingLSI CORP·Filed 2014·Application pending·0 cites
- 2743US8923413B2Optimization of data processors with irregular patternsLSI CORP·Filed 2012·Granted Dec 30, 2014·0 cites·17 claims
- 2843US8868890B2No-delay microsequencerSHUTKIN YURII S·Filed 2011·Granted Oct 21, 2014·0 cites·20 claims
- 2942US9319181B2Parallel decoder for multiple wireless standardsSOKOLOV ANDREY P·Filed 2011·Granted Apr 19, 2016·0 cites·20 claims
- 3042US8923315B2Packet router having a hierarchical buffer structureLSI CORP·Filed 2013·Granted Dec 30, 2014·0 cites·14 claims
- 3139US11095317B2Efficiently decodable QC-LDPC codeHUAWEI TECH CO LTD·Filed 2019·Granted Aug 17, 2021·0 cites·20 claims
- 3238US8775914B2Radix-4 viterbi forward error correction decodingGASANOV ELYAR E·Filed 2011·Granted Jul 8, 2014·0 cites·18 claims
- 3338US8775893B2Variable parity encoderPANTELEEV PAVEL A·Filed 2012·Granted Jul 8, 2014·0 cites·18 claims
- 3438US8700969B2Reconfigurable encoding per multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 3537US8699396B2Branch metrics calculation for multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 3636US2014040342A1High speed add-compare-select circuitLSI CORP·Filed 2013·Application pending·0 cites
- 3736US2014164876A1Modulation coding of parity bits generated using an error-correction codeLSI CORP·Filed 2013·Application pending·0 cites
- 3835US2012166501A1Computation of jacobian logarithm operationSOKOLOV ANDREY P·Filed 2011·Application pending·0 cites
- 3934US8938654B2Programmable circuit for high speed computation of the interleaver tables for multiple wireless standardsSOKOLOV ANDREY P·Filed 2010·Granted Jan 20, 2015·0 cites·20 claims
- 4034US8842784B2L-value generation in a decoderSOKOLOV ANDREY P·Filed 2011·Granted Sep 23, 2014·0 cites·18 claims
- 4131US2015229333A1Systems and Methods for Rank Deficient EncodingLSI CORP·Filed 2014·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →