Inventor · disambiguated record
Derrick Sai-Tang Butt
Also filed as: BUTT DERRICK · BUTT DERRICK S T · BUTT DERRICK SAI-TANG
9 granted patents·1 pending application·123 citations·filing 2004–2012
88Inventor score
Top patents by PatentIndex Score
10 records- 0193US7437500B2Configurable high-speed memory interface subsystemLSI CORP·Filed 2005·Granted Oct 14, 2008·35 cites·18 claims
- 0291US7443741B2DQS strobe centering (data eye training) methodLSI CORP·Filed 2005·Granted Oct 28, 2008·31 cites·20 claims
- 0390US7215584B2Method and/or apparatus for training DQS strobe gatingLSI LOGIC CORP·Filed 2005·Granted May 8, 2007·29 cites·20 claims
- 0478US7865661B2Configurable high-speed memory interface subsystemLSI CORP·Filed 2008·Granted Jan 4, 2011·9 cites·20 claims
- 0568US8819354B2Feedback programmable data strobe enable architecture for DDR memory applicationsSETO HUI-YIN·Filed 2005·Granted Aug 26, 2014·6 cites·20 claims
- 0664US7394707B2Programmable data strobe enable architecture for DDR memory applicationsLSI CORP·Filed 2005·Granted Jul 1, 2008·6 cites·20 claims
- 0763US7969799B2Multiple memory standard physical layer macro functionLSI CORP·Filed 2008·Granted Jun 28, 2011·5 cites·22 claims
- 0848US9257200B2Bit error testing and training in double data rate (DDR) memory systemBHAKTA DHARMESH N·Filed 2012·Granted Feb 9, 2016·1 cites·19 claims
- 0939US2005229132A1Macro cell for integrated circuit physical layer interfaceLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1037US8098073B2System for terminating high speed input/output buffers in an automatic test equipment environment to enable external loopback testingBUTT DERRICK SAI-TANG·Filed 2007·Granted Jan 17, 2012·1 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →