Inventor · disambiguated record
Wei-Jin Dai
Also filed as: DAI WEI · DAI WEI-JIN
13 granted patents·1 pending application·1,200 citations·filing 1993–2022
94Inventor score
Files withCADENCE DESIGN SYSTEMS INC4SILICON PERSPECTIVE CORP3VISA INT SERVICE ASS3QUICKTURN DESIGN SYSTEMS INC2WU PING-CHIH1
Top patents by PatentIndex Score
14 records- 0194US6249902B1Design hierarchy-based placementSILICON PERSPECTIVE CORP·Filed 1998·Granted Jun 19, 2001·451 cites·15 claims
- 0294US5452239AMethod of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation systemQUICKTURN DESIGN SYSTEMS INC·Filed 1993·Granted Sep 19, 1995·436 cites·2 claims
- 0390US11804960B2Distributed symmetric encryptionVISA INT SERVICE ASS·Filed 2022·Granted Oct 31, 2023·2 cites·16 claims
- 0486US6519749B1Integrated circuit partitioning placement and routing systemSILICON PERSPECTIVE CORP·Filed 2000·Granted Feb 11, 2003·60 cites·23 claims
- 0585US6782520B1IC layout system having separate trial and detailed routing phasesCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 24, 2004·50 cites·21 claims
- 0685US6651235B2Scalable, partitioning integrated circuit layout systemCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Nov 18, 2003·52 cites·32 claims
- 0783US6751786B2Clock tree synthesis for a hierarchically partitioned IC layoutCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jun 15, 2004·41 cites·15 claims
- 0881US6782519B2Clock tree synthesis for mixed domain clocksCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 24, 2004·36 cites·14 claims
- 0980US6578183B2Method for generating a partitioned IC layoutSILICON PERSPECTIVE CORP·Filed 2001·Granted Jun 10, 2003·36 cites·21 claims
- 1074US8095898B1Method and system for implementing electronic design entryWU PING-CHIH·Filed 2007·Granted Jan 10, 2012·13 cites·26 claims
- 1154US11438152B2Distributed symmetric encryptionVISA INT SERVICE ASS·Filed 2020·Granted Sep 6, 2022·0 cites·18 claims
- 1246US11818263B2Computing key rotation period for block cipher-based encryption schemes system and methodVISA INT SERVICE ASS·Filed 2019·Granted Nov 14, 2023·0 cites·15 claims
- 1343US5886904ALatch optimization in hardware logic emulation systemsQUICKTURN DESIGN SYSTEMS INC·Filed 1996·Granted Mar 23, 1999·23 cites·16 claims
- 1442US2003135836A1Gated clock tree synthesisFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →