Inventor · disambiguated record
John A. Waicukauski
Also filed as: WAICUKAUSKI JOHN · WAICUKAUSKI JOHN A · WAICUKAUSKI JOHN ARTHUR
30 granted patents·1,047 citations·filing 1985–2023
97Inventor score
Top patents by PatentIndex Score
30 records- 0197US6950974B1Efficient compression and application of deterministic patterns in a logic BIST architectureSYNOPSYS INC·Filed 2001·Granted Sep 27, 2005·92 cites·30 claims
- 0296US7823034B2Pipeline of additional storage elements to shift input/output data of combinational scan compression circuitSYNOPSYS INC·Filed 2007·Granted Oct 26, 2010·41 cites·15 claims
- 0396US7237162B1Deterministic BIST architecture tolerant of uncertain scan chain outputsSYNOPSYS INC·Filed 2002·Granted Jun 26, 2007·69 cites·12 claims
- 0496US4801870AWeighted random pattern testing apparatus and methodIBM·Filed 1988·Granted Jan 31, 1989·154 cites·4 claims
- 0594US6993694B1Deterministic bist architecture including MISR filterSYNOPSYS INC·Filed 2002·Granted Jan 31, 2006·75 cites·12 claims
- 0694US4687988AWeighted random pattern testing apparatus and methodIBM·Filed 1985·Granted Aug 18, 1987·133 cites·3 claims
- 0793US6807646B1System and method for time slicing deterministic patterns for reseeding in logic built-in self-testSYNOPSYS INC·Filed 2002·Granted Oct 19, 2004·61 cites·26 claims
- 0893US5612963AHybrid pattern self-testing of integrated circuitsIBM·Filed 1995·Granted Mar 18, 1997·108 cites·13 claims
- 0992US6385750B1Method and system for controlling test data volume in deterministic test pattern generationSYNOPSYS INC·Filed 1999·Granted May 7, 2002·97 cites·30 claims
- 1090US8645780B2Fully X-tolerant, very high scan compression scan test systems and techniquesSYNOPSYS INC·Filed 2013·Granted Feb 4, 2014·6 cites·7 claims
- 1188US10908213B1Reducing X-masking effect for linear time compactorsSYNOPSYS INC·Filed 2019·Granted Feb 2, 2021·3 cites·51 claims
- 1288US7979763B2Fully X-tolerant, very high scan compression scan test systems and techniquesSYNOPSYS INC·Filed 2009·Granted Jul 12, 2011·12 cites·20 claims
- 1387US4745355AWeighted random pattern testing apparatus and methodIBM·Filed 1987·Granted May 17, 1988·58 cites·6 claims
- 1485US4688223AWeighted random pattern testing apparatus and methodIBM·Filed 1985·Granted Aug 18, 1987·49 cites·3 claims
- 1583US7814444B2Scan compression circuit and method of design thereforSYNOPSYS INC·Filed 2007·Granted Oct 12, 2010·16 cites·17 claims
- 1679US8464115B2Fully X-tolerant, very high scan compression scan test systems and techniquesWOHL PETER·Filed 2011·Granted Jun 11, 2013·3 cites·9 claims
- 1779US7958472B2Increasing scan compression by using X-chainsSYNOPSYS INC·Filed 2008·Granted Jun 7, 2011·10 cites·16 claims
- 1878US9157961B2Two-level compression through selective reseedingSYNOPSYS INC·Filed 2013·Granted Oct 13, 2015·4 cites·26 claims
- 1977US7882410B2Launch-on-shift support for on-chip-clockingSYNOPSYS INC·Filed 2007·Granted Feb 1, 2011·9 cites·22 claims
- 2076US12117488B1Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)SYNOPSYS INC·Filed 2023·Granted Oct 15, 2024·0 cites·20 claims
- 2169US8429473B2Increasing PRPG-based compression by delayed justificationWOHL PETER·Filed 2010·Granted Apr 23, 2013·2 cites·23 claims
- 2264US9171123B2Diagnosis and debug using truncated simulationSYNOPSYS INC·Filed 2013·Granted Oct 27, 2015·1 cites·33 claims
- 2362US12277372B2Multi-cycle test generation and source-based simulationSYNOPSYS INC·Filed 2022·Granted Apr 15, 2025·0 cites·20 claims
- 2462US8549372B2ATPG and compression by using majority gatesWOHL PETER·Filed 2012·Granted Oct 1, 2013·1 cites·26 claims
- 2558US11422186B1Per-shift X-tolerant logic built-in self-testSYNOPSYS INC·Filed 2020·Granted Aug 23, 2022·0 cites·16 claims
- 2658US6453437B1Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Sep 17, 2002·32 cites·15 claims
- 2757US9404972B2Diagnosis and debug with truncated simulationSYNOPSYS INC·Filed 2015·Granted Aug 2, 2016·0 cites·38 claims
- 2855US9152752B2Increasing PRPG-based compression by delayed justificationSYNOPSYS INC·Filed 2013·Granted Oct 6, 2015·0 cites·22 claims
- 2947US10346557B2Increasing compression by reducing padding patternsSYNOPSYS INC·Filed 2017·Granted Jul 9, 2019·0 cites·27 claims
- 3041US6959272B2Method and system for generating an ATPG model of a memory from behavioral descriptionsSYNOPSYS INC·Filed 1999·Granted Oct 25, 2005·11 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →