Inventor · disambiguated record
Ian A. Buck
Also filed as: BUCK IAN · BUCK IAN A · BUCK IAN ANDREW
17 granted patents·5 pending applications·547 citations·filing 2004–2023
94Inventor score
Top patents by PatentIndex Score
22 records- 0198US7627723B1Atomic memory operators in a parallel processorNVIDIA CORP·Filed 2006·Granted Dec 1, 2009·167 cites·20 claims
- 0297US7219085B2System and method for accelerating and optimizing the processing of machine learning techniques using a graphics processing unitMICROSOFT CORP·Filed 2004·Granted May 15, 2007·144 cites·35 claims
- 0396US8321849B2Virtual architecture and instruction set for parallel thread computingNICKOLLS JOHN R·Filed 2007·Granted Nov 27, 2012·88 cites·23 claims
- 0492US8402229B1System and method for enabling interoperability between application programming interfacesWILT NICHOLAS PATRICK·Filed 2008·Granted Mar 19, 2013·14 cites·22 claims
- 0587US7567252B2Optimizing performance of a graphics processing unit for efficient execution of general matrix operationsMICROSOFT CORP·Filed 2004·Granted Jul 28, 2009·43 cites·15 claims
- 0687US7548892B2Processing machine learning techniques using a graphics processing unitMICROSOFT CORP·Filed 2007·Granted Jun 16, 2009·30 cites·20 claims
- 0783US8539516B1System and method for enabling interoperability between application programming interfacesWILT NICHOLAS PATRICK·Filed 2008·Granted Sep 17, 2013·14 cites·14 claims
- 0876US8276132B1System and method for representing and managing a multi-architecture co-processor application programVANDERSPEK JULIUS·Filed 2007·Granted Sep 25, 2012·8 cites·20 claims
- 0976US8271763B2Unified addressing and instructions for accessing parallel memory spacesNICKOLLS JOHN R·Filed 2009·Granted Sep 18, 2012·7 cites·20 claims
- 1076US7809928B1Generating event signals for performance register control using non-operative instructionsNVIDIA CORP·Filed 2005·Granted Oct 5, 2010·8 cites·18 claims
- 1175US8347310B1System and method for representing and managing a multi-architecure co-processor application programNVIDIA CORP·Filed 2007·Granted Jan 1, 2013·7 cites·18 claims
- 1274US9542192B1Tokenized streams for concurrent execution between asymmetric multiprocessorsWILT NICHOLAS PATRICK·Filed 2008·Granted Jan 10, 2017·7 cites·14 claims
- 1369US8281294B1System and method for representing and managing a multi-architecture co-processor application programVANDERSPEK JULIUS·Filed 2007·Granted Oct 2, 2012·5 cites·20 claims
- 1465US8261234B1System, method, and computer program product for compiling code adapted to execute utilizing a first processor, for executing the code utilizing a second processorAARTS BASTIAAN J M·Filed 2008·Granted Sep 4, 2012·5 cites·15 claims
- 1560US12320040B2Woven structure and method of manufactureROLLS ROYCE PLC·Filed 2023·Granted Jun 3, 2025·0 cites·7 claims
- 1657US12257763B2Woven structure, method and apparatus for a flanged composite componentROLLS ROYCE PLC·Filed 2023·Granted Mar 25, 2025·0 cites·8 claims
- 1755US2024017503A1Woven fabrics for composite componentsROLLS ROYCE PLC·Filed 2023·Application pending·0 cites
- 1853US2024117533A1Woven structure and method of manufactureROLLS ROYCE PLC·Filed 2023·Application pending·0 cites
- 1950US2024018702A1Woven fabrics for composite componentsROLLS ROYCE PLC·Filed 2023·Application pending·0 cites
- 2048US9317290B2Expressing parallel execution relationships in a sequential programming languageNVIDIA CORP·Filed 2013·Granted Apr 19, 2016·0 cites·16 claims
- 2148US2008109795A1C/c++ language extensions for general-purpose graphics processing unitNVIDIA CORP·Filed 2006·Application pending·0 cites
- 2245US2012066668A1C/c++ language extensions for general-purpose graphics processing unitBUCK IAN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →