Inventor · disambiguated record
Mark A. Bordogna
Also filed as: BORDOGNA MARK · BORDOGNA MARK A · BORDOGNA MARK ALDO
25 granted patents·12 pending applications·316 citations·filing 1997–2024
95Inventor score
Top patents by PatentIndex Score
37 records- 0188US12222750B2Timestamp alignment across multiple computing nodesINTEL CORP·Filed 2023·Granted Feb 11, 2025·1 cites·21 claims
- 0285US10931391B2One-step time stamping of synchronization packets for networked devicesINTEL CORP·Filed 2017·Granted Feb 23, 2021·5 cites·20 claims
- 0384US6366556B1Self-healing networks using virtual ringsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Apr 2, 2002·93 cites·21 claims
- 0483US11265096B2High accuracy time stamping for multi-lane portsINTEL CORP·Filed 2019·Granted Mar 1, 2022·4 cites·20 claims
- 0579US11693448B2Timestamp alignment across multiple computing nodesINTEL CORP·Filed 2019·Granted Jul 4, 2023·2 cites·25 claims
- 0675US11212024B2Technologies for high-precision timestamping of packetsINTEL CORP·Filed 2017·Granted Dec 28, 2021·2 cites·19 claims
- 0773US6683855B1Forward error correction for high speed optical transmission systemsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jan 27, 2004·87 cites·27 claims
- 0872US2025088342A1Timestamp alignment for multiple nodesINTEL CORP·Filed 2024·Application pending·0 cites
- 0969US11805042B2Technologies for timestamping with error correctionINTEL CORP·Filed 2022·Granted Oct 31, 2023·0 cites·20 claims
- 1066US11546241B2Technologies for timestamping with error correctionINTEL CORP·Filed 2021·Granted Jan 3, 2023·0 cites·19 claims
- 1166US10509435B2Protected real time clock with hardware interconnectsINTEL CORP·Filed 2016·Granted Dec 17, 2019·1 cites·25 claims
- 1264US7593327B2Method and apparatus for frequency offset control of ethernet packets over a transport networkAGERE SYSTEMS INC·Filed 2003·Granted Sep 22, 2009·13 cites·20 claims
- 1362US12160495B2Timestamp alignment for multiple nodesINTEL CORP·Filed 2021·Granted Dec 3, 2024·0 cites·18 claims
- 1460US11711159B2High accuracy time stamping for multi-lane portsINTEL CORP·Filed 2020·Granted Jul 25, 2023·0 cites·15 claims
- 1560US11671194B2Technologies for high-precision timestamping of packetsINTEL CORP·Filed 2021·Granted Jun 6, 2023·0 cites·16 claims
- 1657US6560202B1Control architecture using a multi-layer embedded signal status protocolLUCENT TECHNOLOGIES INC·Filed 1998·Granted May 6, 2003·22 cites·24 claims
- 1755US11153191B2Technologies for timestamping with error correctionINTEL CORP·Filed 2018·Granted Oct 19, 2021·0 cites·21 claims
- 1854US7813285B2Method for per-port flow control of packets aggregated from multiple logical ports over a transport linkAGERE SYSTEMS INC·Filed 2008·Granted Oct 12, 2010·1 cites·19 claims
- 1954US6091731ADuplication in asychronous transfer mode (ATM) network fabricsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jul 18, 2000·40 cites·1 claims
- 2053US12177003B2Method and apparatus for data plane control of network time sync protocol in multi-host systemsINTEL CORP·Filed 2021·Granted Dec 24, 2024·0 cites·20 claims
- 2151US2025125896A1Network-based time synchronizationINTEL CORP·Filed 2024·Application pending·0 cites
- 2251US2023370241A1Time synchronization technologiesINTEL CORP·Filed 2023·Application pending·0 cites
- 2349US2023077631A1Time domain monitoring and adjustment by a network interface deviceINTEL CORP·Filed 2022·Application pending·0 cites
- 2448US2010329245A1Transparent Mapping of Cell Streams to Packet ServicesBORDOGNA MARK A·Filed 2009·Application pending·0 cites
- 2547US8005094B2Method and apparatus for circuit emulation services over cell and packet networksAGERE SYSTEMS INC·Filed 2006·Granted Aug 23, 2011·0 cites·24 claims
- 2647US2024204899A1Phase synchronization between timersINTEL CORP·Filed 2024·Application pending·0 cites
- 2743US2022337683A1Multiple time domain network device translationINTEL CORP·Filed 2021·Application pending·0 cites
- 2843US2023344739A1Methods and apparatus to generate an egress timestampPERI SUREKHA·Filed 2023·Application pending·0 cites
- 2941US2014254735A1Transmit reference signal cleanup within a synchronous network applicationLSI CORP·Filed 2013·Application pending·0 cites
- 3040US2006013210A1Method and apparatus for per-service fault protection and restoration in a packet networkBORDOGNA MARK A·Filed 2004·Application pending·0 cites
- 3139US2015055644A1Precise timestamping of ethernet packets by compensating for start-of-frame delimiter detection delay and delay variationsLSI CORP·Filed 2013·Application pending·0 cites
- 3238US6301228B1Method and apparatus for switching signals using an embedded group signal statusLUCENT TECHNOLOGIES INC·Filed 1998·Granted Oct 9, 2001·12 cites·24 claims
- 3338US6081503AControl architecture using an embedded signal status protocolLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jun 27, 2000·13 cites·19 claims
- 3438US2004085904A1Method for flow control of packets aggregated from multiple logical ports over a transport linkFiled 2002·Application pending·0 cites
- 3537US9065761B2Packet reassembly processingMUNOZ ROBERT J·Filed 2011·Granted Jun 23, 2015·0 cites·11 claims
- 3637US6091730AControl of asynchronous transfer mode (ATM) switching networksLUCENT TECHNOLOGIES INC·Filed 1998·Granted Jul 18, 2000·15 cites·5 claims
- 3731US6137790AControl architecture for a homogeneous routing structureLUCENT TECHNOLOGIES INC·Filed 1997·Granted Oct 24, 2000·5 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →