Inventor · disambiguated record
Lily P. Looi
Also filed as: LOOI LILY · LOOI LILY P · LOOI LILY PAO
35 granted patents·8 pending applications·590 citations·filing 1996–2019
97Inventor score
Top patents by PatentIndex Score
43 records- 0192US6971098B2Method and apparatus for managing transaction requests in a multi-node architectureINTEL CORP·Filed 2001·Granted Nov 29, 2005·88 cites·29 claims
- 0292US6615319B2Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architectureINTEL CORP·Filed 2000·Granted Sep 2, 2003·95 cites·21 claims
- 0390US6810467B1Method and apparatus for centralized snoop filteringINTEL CORP·Filed 2000·Granted Oct 26, 2004·72 cites·16 claims
- 0488US8275560B2Power measurement techniques of a system-on-chip (SOC)RADHAKRISHNAN SIVAKUMAR·Filed 2009·Granted Sep 25, 2012·17 cites·24 claims
- 0587US6842830B2Mechanism for handling explicit writeback in a cache coherent multi-node architectureINTEL CORP·Filed 2001·Granted Jan 11, 2005·39 cites·9 claims
- 0686US8782456B2Dynamic and idle power reduction sequence using recombinant clock and power gatingTAN SIN S·Filed 2010·Granted Jul 15, 2014·10 cites·30 claims
- 0782US7996625B2Method and apparatus for reducing memory latency in a cache coherent multi-node architectureINTEL CORP·Filed 2007·Granted Aug 9, 2011·10 cites·8 claims
- 0880US7234029B2Method and apparatus for reducing memory latency in a cache coherent multi-node architectureINTEL CORP·Filed 2000·Granted Jun 19, 2007·27 cites·27 claims
- 0979US7124252B1Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor systemINTEL CORP·Filed 2000·Granted Oct 17, 2006·28 cites·26 claims
- 1076US8850250B2Integration of processor and input/output hubLOOI LILY PAO·Filed 2010·Granted Sep 30, 2014·6 cites·20 claims
- 1176US6772298B2Method and apparatus for invalidating a cache line without data return in a multi-node architectureINTEL CORP·Filed 2000·Granted Aug 3, 2004·24 cites·19 claims
- 1274US9910814B2Method, apparatus and system for single-ended communication of transaction layer packetsINTEL CORP·Filed 2015·Granted Mar 6, 2018·2 cites·17 claims
- 1374US7093079B2Snoop filter bypassINTEL CORP·Filed 2002·Granted Aug 15, 2006·19 cites·19 claims
- 1473US9021156B2Integrating intellectual property (IP) blocks into a processorNIMMALA PRASHANTH·Filed 2011·Granted Apr 28, 2015·6 cites·19 claims
- 1570US7383398B2Preselecting E/M line replacement technique for a snoop filterINTEL CORP·Filed 2006·Granted Jun 3, 2008·5 cites·20 claims
- 1669US6859864B2Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache lineINTEL CORP·Filed 2000·Granted Feb 22, 2005·14 cites·19 claims
- 1767US7167957B2Mechanism for handling explicit writeback in a cache coherent multi-node architectureINTEL CORP·Filed 2004·Granted Jan 23, 2007·9 cites·11 claims
- 1862US8539260B2Method, apparatus, and system for enabling platform power statesBILGIN SELIM·Filed 2010·Granted Sep 17, 2013·2 cites·13 claims
- 1961US9146610B2Throttling integrated linkRAJWAR RAVI·Filed 2011·Granted Sep 29, 2015·1 cites·19 claims
- 2060US5987552ABus protocol for atomic transactionsINTEL CORP·Filed 1998·Granted Nov 16, 1999·37 cites·28 claims
- 2158US7617329B2Programmable protocol to support coherent and non-coherent transactions in a multinode systemINTEL CORP·Filed 2002·Granted Nov 10, 2009·6 cites·30 claims
- 2257US6976129B2Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architectureINTEL CORP·Filed 2002·Granted Dec 13, 2005·5 cites·21 claims
- 2356US9952644B2Device power management state transition latency advertisement for faster boot timeINTEL CORP·Filed 2015·Granted Apr 24, 2018·0 cites·10 claims
- 2456US9952643B2Device power management state transition latency advertisement for faster boot timeINTEL CORP·Filed 2015·Granted Apr 24, 2018·0 cites·8 claims
- 2556US6622215B2Mechanism for handling conflicts in a multi-node computer architectureINTEL CORP·Filed 2000·Granted Sep 16, 2003·4 cites·15 claims
- 2654US2014281639A1Device power management state transition latency advertisement for faster boot timeWAGH MAHESH·Filed 2013·Application pending·0 cites
- 2753US10949356B2Fast page fault handling process implemented on persistent memoryINTEL CORP·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 2853US10496152B2Power control techniques for integrated PCIe controllersINTEL CORP·Filed 2013·Granted Dec 3, 2019·0 cites·25 claims
- 2953US10241952B2Throttling integrated linkINTEL CORP·Filed 2015·Granted Mar 26, 2019·0 cites·21 claims
- 3052US9537665B2Method, apparatus, and system for enabling platform power statesINTEL CORP·Filed 2013·Granted Jan 3, 2017·0 cites·27 claims
- 3150US7376775B2Apparatus, system, and method to enable transparent memory hot plug/removeINTEL CORP·Filed 2003·Granted May 20, 2008·2 cites·24 claims
- 3249US11029744B2System, apparatus and method for controlling a processor based on effective stress informationINTEL CORP·Filed 2017·Granted Jun 8, 2021·0 cites·21 claims
- 3349US2006106993A1Mechanism for handling explicit writeback in a cache coherent multi-node architectureKHARE MANOJ·Filed 2005·Application pending·0 cites
- 3446US5996038AIndividually resettable bus expander bridge mechanismINTEL CORP·Filed 1998·Granted Nov 30, 1999·18 cites·21 claims
- 3544US6134632AController that supports data merging utilizing a slice addressable memory arrayINTEL CORP·Filed 1998·Granted Oct 17, 2000·19 cites·24 claims
- 3642US6195722B1Method and apparatus for deferring transactions on a host bus having a third party agentINTEL CORP·Filed 1998·Granted Feb 27, 2001·16 cites·19 claims
- 3742US2007233965A1Way hint line replacement algorithm for a snoop filterCHENG KAI·Filed 2006·Application pending·0 cites
- 3842US2004128351A1Mechanism to broadcast transactions to multiple agents in a multi-node systemINTEL CORP·Filed 2002·Application pending·0 cites
- 3941US2002087775A1Apparatus and method for interrupt deliveryFiled 2000·Application pending·0 cites
- 4041US2002087765A1Method and system for completing purge requests or the like in a multi-node multiprocessor systemFiled 2000·Application pending·0 cites
- 4140US2003131201A1Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory systemFiled 2000·Application pending·0 cites
- 4238US2002087766A1Method and apparatus to implement a locked-bus transactionFiled 2000·Application pending·0 cites
- 4336US5930486AMethod and device for gracious arbitration of access to a computer system resourceINTEL CORP·Filed 1996·Granted Jul 27, 1999·9 cites·12 claims
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