Inventor · disambiguated record
Douglas C. La Tulipe, Jr.
Also filed as: LA TULIPE DOUGLAS · LA TULIPE DOUGLAS C · LA TULIPE DOUGLAS C JR · LA TULIPE DOUGLAS CHARLES
52 granted patents·8 pending applications·929 citations·filing 2002–2025
98Inventor score
Files withIBM27UNIV NEW YORK STATE RES FOUND10LA TULIPE JR DOUGLAS C5INFINEON TECHNOLOGIES AG3BERLINER NATHANIEL C2
Top patents by PatentIndex Score
60 records- 0199US7666723B2Methods of forming wiring to transistor and related transistorIBM·Filed 2007·Granted Feb 23, 2010·271 cites·17 claims
- 0298US9620481B2Substrate bonding with diffusion barrier structuresGLOBALFOUNDRIES INC·Filed 2015·Granted Apr 11, 2017·220 cites·16 claims
- 0397US10698156B2Wafer scale bonded active photonics interposerUNIV NEW YORK STATE RES FOUND·Filed 2018·Granted Jun 30, 2020·19 cites·30 claims
- 0496US11435523B2Wafer scale bonded active photonics interposerUNIV NEW YORK STATE RES FOUND·Filed 2020·Granted Sep 6, 2022·3 cites·21 claims
- 0596US10976491B2Photonics interposer optoelectronicsUNIV NEW YORK STATE RES FOUND·Filed 2017·Granted Apr 13, 2021·35 cites·20 claims
- 0696US9064937B2Substrate bonding with diffusion barrier structuresIBM·Filed 2013·Granted Jun 23, 2015·29 cites·11 claims
- 0796US9029238B2Advanced handler wafer bonding and debondingIBM·Filed 2012·Granted May 12, 2015·26 cites·20 claims
- 0896US8390079B2Sealed air gap for semiconductor chipHORAK DAVID V·Filed 2010·Granted Mar 5, 2013·26 cites·4 claims
- 0996US8232618B2Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approachBREYTA GREGORY·Filed 2010·Granted Jul 31, 2012·33 cites·12 claims
- 1095US8900885B1Wafer bonding misalignment reductionIBM·Filed 2013·Granted Dec 2, 2014·22 cites·20 claims
- 1194US11550173B2Heterogeneous structure on an integrated photonics platformUNIV NEW YORK STATE RES FOUND·Filed 2020·Granted Jan 10, 2023·3 cites·20 claims
- 1294US10877300B2Heterogeneous structure on an integrated photonics platformUNIV NEW YORK STATE RES FOUND·Filed 2019·Granted Dec 29, 2020·7 cites·28 claims
- 1394US8946007B2Inverted thin channel mosfet with self-aligned expanded source/drainIBM·Filed 2013·Granted Feb 3, 2015·17 cites·11 claims
- 1491US9583628B2Semiconductor device with a low-K spacer and method of forming the sameGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 28, 2017·6 cites·18 claims
- 1591US8765578B2Edge protection of bonded wafers during wafer thinningLA TULIPE JR DOUGLAS C·Filed 2012·Granted Jul 1, 2014·16 cites·17 claims
- 1690US9034701B2Semiconductor device with a low-k spacer and method of forming the sameCHENG KANGGUO·Filed 2012·Granted May 19, 2015·9 cites·9 claims
- 1789US11029466B2Photonics structure with integrated laserUNIV NEW YORK STATE RES FOUND·Filed 2019·Granted Jun 8, 2021·9 cites·28 claims
- 1889US8871624B2Sealed air gap for semiconductor chipIBM·Filed 2013·Granted Oct 28, 2014·8 cites·15 claims
- 1989US7241681B2Bilayered metal hardmasks for use in dual damascene etch schemesIBM·Filed 2006·Granted Jul 10, 2007·13 cites·8 claims
- 2088US7723851B2Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasIBM·Filed 2007·Granted May 25, 2010·17 cites·10 claims
- 2187US11550099B2Photonics optoelectrical systemUNIV NEW YORK STATE RES FOUND·Filed 2019·Granted Jan 10, 2023·5 cites·20 claims
- 2286US9059039B2Reducing wafer bonding misalignment by varying thermal treatment prior to bondingIBM·Filed 2013·Granted Jun 16, 2015·6 cites·15 claims
- 2384US9219129B2Inverted thin channel mosfet with self-aligned expanded source/drainDORIS BRUCE B·Filed 2012·Granted Dec 22, 2015·6 cites·12 claims
- 2481US7875528B2Method, system, program product for bonding two circuitry-including substrates and related stageIBM·Filed 2007·Granted Jan 25, 2011·7 cites·6 claims
- 2580US7488630B2Method for preparing 2-dimensional semiconductor devices for integration in a third dimensionIBM·Filed 2007·Granted Feb 10, 2009·9 cites·13 claims
- 2680US7122462B2Back end interconnect with a shaped interfaceINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 17, 2006·25 cites·5 claims
- 2779US9536809B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2015·Granted Jan 3, 2017·3 cites·3 claims
- 2877US7704869B2Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasIBM·Filed 2007·Granted Apr 27, 2010·7 cites·16 claims
- 2976US11841531B2Wafer scale bonded active photonics interposerUNIV NEW YORK STATE RES FOUND·Filed 2022·Granted Dec 12, 2023·0 cites·20 claims
- 3076US7528056B2Low-cost strained SOI substrate for high-performance CMOS technologyIBM·Filed 2007·Granted May 5, 2009·5 cites·16 claims
- 3176US7052621B2Bilayered metal hardmasks for use in Dual Damascene etch schemesIBM·Filed 2003·Granted May 30, 2006·15 cites·15 claims
- 3276US2025377497A1Photonics optoelectrical systemUNIV NEW YORK STATE RES FOUND·Filed 2025·Application pending·0 cites
- 3373US8592270B2Non-relaxed embedded stressors with solid source extension regions in CMOS devicesCHENG KANGGUO·Filed 2011·Granted Nov 26, 2013·3 cites·9 claims
- 3473US7955967B2Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasIBM·Filed 2009·Granted Jun 7, 2011·5 cites·13 claims
- 3573US7241696B2Method for depositing a metal layer on a semiconductor interconnect structure having a capping layerINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jul 10, 2007·20 cites·19 claims
- 3670US12366705B2Photonics optoelectrical systemUNIV NEW YORK STATE RES FOUND·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 3769US9543229B2Combination of TSV and back side wiring in 3D integrationIBM·Filed 2013·Granted Jan 10, 2017·2 cites·6 claims
- 3864US8637358B1Field-effect-transistor with self-aligned diffusion contactKOBURGER III CHARLES WILLIAM·Filed 2012·Granted Jan 28, 2014·2 cites·17 claims
- 3964US8124427B2Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thicknessBERLINER NATHANIEL C·Filed 2009·Granted Feb 28, 2012·2 cites·20 claims
- 4062US7125792B2Dual damascene structure and methodIBM·Filed 2003·Granted Oct 24, 2006·8 cites·24 claims
- 4161US9318375B2Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep viasLA TULIPE JR DOUGLAS C·Filed 2009·Granted Apr 19, 2016·2 cites·11 claims
- 4258US12494424B2Interconnect structure of a semiconductor component and methods for producing the structureIMEC VZW·Filed 2022·Granted Dec 9, 2025·0 cites·9 claims
- 4358US7091612B2Dual damascene structure and methodIBM·Filed 2003·Granted Aug 15, 2006·8 cites·26 claims
- 4456US9412620B2Three-dimensional integrated circuit device fabrication including wafer scale membraneGLOBALFOUNDRIES US 2 LLC·Filed 2015·Granted Aug 9, 2016·0 cites·14 claims
- 4556US8963278B2Three-dimensional integrated circuit device using a wafer scale membraneIBM·Filed 2013·Granted Feb 24, 2015·0 cites·7 claims
- 4653US11886014B2Two-stage expanded beam optical couplingIMEC VZW·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 4752US8637953B2Wafer scale membrane for three-dimensional integrated circuit device fabricationLA TULIPE JR DOUGLAS C·Filed 2008·Granted Jan 28, 2014·0 cites·5 claims
- 4852US2012299145A1Apparatus for three-dimensional integrated circuit device fabrication including wafer scale membraneLA TULIPE JR DOUGLAS C·Filed 2012·Application pending·0 cites
- 4952US2012302040A1Method of fabrication of a three-dimensional integrated circuit device using a wafer scale membraneLA TULIPE JR DOUGLAS C·Filed 2012·Application pending·0 cites
- 5050US8940554B2Method of creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thicknessBERLINER NATHANIEL C·Filed 2012·Granted Jan 27, 2015·0 cites·16 claims
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