Inventor · disambiguated record
Jeffrey G. Wiedemeier
Also filed as: WIEDEMEIER JEFFREY · WIEDEMEIER JEFFREY G · WIEDEMEIER JEFFREY GORDON
14 granted patents·9 pending applications·144 citations·filing 2000–2024
90Inventor score
Files withINTEL CORP14HUGHES CHRISTOPHER J3ADRIAN JESUS CORBAL SAN1COMBS JONATHAN D1HEWLETT PACKARD DEVELOPMENT CO1
Top patents by PatentIndex Score
23 records- 0193US8447962B2Gathering and scattering multiple data elementsHUGHES CHRISTOPHER J·Filed 2009·Granted May 21, 2013·36 cites·30 claims
- 0292US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 0391US8972698B2Vector conflict instructionsHUGHES CHRISTOPHER J·Filed 2010·Granted Mar 3, 2015·18 cites·23 claims
- 0489US6715057B1Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizesHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 30, 2004·74 cites·8 claims
- 0588US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 0684US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 0777US12505000B2Software visible and controllable lock-stepping with configurable logical processor granularitiesINTEL CORP·Filed 2024·Granted Dec 23, 2025·0 cites·20 claims
- 0877US10037205B2Instruction and logic to provide vector blend and permute functionalityVALENTINE ROBERT·Filed 2011·Granted Jul 31, 2018·5 cites·28 claims
- 0976US11740904B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 1073US11210096B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2020·Granted Dec 28, 2021·0 cites·28 claims
- 1166US10795680B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2019·Granted Oct 6, 2020·0 cites·9 claims
- 1264US12086653B2Software visible and controllable lock-stepping with configurable logical processor granularitiesINTEL CORP·Filed 2020·Granted Sep 10, 2024·0 cites·24 claims
- 1360US9329865B2Context control and parameter passing within microcode based instruction routinesCOMBS JONATHAN D·Filed 2013·Granted May 3, 2016·1 cites·20 claims
- 1458US2019108029A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 1558US2019108030A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskINTEL CORP·Filed 2018·Application pending·0 cites
- 1655US10175990B2Gathering and scattering multiple data elementsINTEL CORP·Filed 2013·Granted Jan 8, 2019·0 cites·25 claims
- 1755US10114651B2Gathering and scattering multiple data elementsHUGHES CHRISTOPHER J·Filed 2018·Granted Oct 30, 2018·0 cites·10 claims
- 1852US2025005157A1System and method for authenticating extended service microcode updatesINTEL CORP·Filed 2023·Application pending·0 cites
- 1951US2013305020A1Vector friendly instruction format and execution thereofVALENTINE ROBERT C·Filed 2011·Application pending·0 cites
- 2049US2012254588A1Systems, apparatuses, and methods for blending two source operands into a single destination using a writemaskADRIAN JESUS CORBAL SAN·Filed 2011·Application pending·0 cites
- 2149US2024069913A1Uniform Microcode Update EnumerationINTEL CORP·Filed 2022·Application pending·0 cites
- 2240US2019004788A1Secure microcode updateINTEL CORP·Filed 2017·Application pending·0 cites
- 2339US2012254592A1Systems, apparatuses, and methods for expanding a memory source into a destination register and compressing a source register into a destination memory locationSAN ADRIAN JESUS CORBAL·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →