Inventor · disambiguated record
Jayesh Iyer
Also filed as: IYER JAYESH
17 granted patents·4 pending applications·26 citations·filing 2010–2018
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0188US10324724B2Hardware apparatuses and methods to fuse instructionsINTEL CORP·Filed 2015·Granted Jun 18, 2019·7 cites·24 claims
- 0273US9858226B2Two wire serial voltage identification protocolIYER JAYESH·Filed 2012·Granted Jan 2, 2018·4 cites·14 claims
- 0370US10133582B2Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processorINTEL CORP·Filed 2013·Granted Nov 20, 2018·3 cites·20 claims
- 0468US10095623B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2016·Granted Oct 9, 2018·1 cites·24 claims
- 0568US8412976B2Data negotiation using serial voltage identification communicationKRAIPAK WASEEM S·Filed 2010·Granted Apr 2, 2013·3 cites·16 claims
- 0667US9904546B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2015·Granted Feb 27, 2018·1 cites·20 claims
- 0765US9645819B2Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processorIYER JAYESH·Filed 2012·Granted May 9, 2017·3 cites·30 claims
- 0863US9471501B2Hardware apparatuses and methods to control access to a multiple bank data cacheINTEL CORP·Filed 2014·Granted Oct 18, 2016·1 cites·24 claims
- 0962US9632790B2Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program orderINTEL CORP·Filed 2012·Granted Apr 25, 2017·2 cites·21 claims
- 1058US10884735B2Instruction and logic for predication and implicit destinationINTEL CORP·Filed 2018·Granted Jan 5, 2021·0 cites·20 claims
- 1158US8417986B2Time negotiation using serial voltage identification communicationKRAIPAK WASEEM S·Filed 2010·Granted Apr 9, 2013·1 cites·12 claims
- 1247US2016179538A1Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processorINTEL CORP·Filed 2014·Application pending·0 cites
- 1346US10235171B2Method and apparatus to efficiently handle allocation of memory ordering buffers in a multi-strand out-of-order loop processorINTEL CORP·Filed 2016·Granted Mar 19, 2019·0 cites·20 claims
- 1444US10241801B2Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·22 claims
- 1544US2016306742A1Instruction and logic for memory access in a clustered wide-execution machineINTEL CORP·Filed 2013·Application pending·0 cites
- 1643US10241794B2Apparatus and methods to support counted loop exits in a multi-strand loop processorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1743US10241789B2Method to do control speculation on loads in a high performance strand-based loop acceleratorINTEL CORP·Filed 2016·Granted Mar 26, 2019·0 cites·20 claims
- 1839US10346170B2Performing partial register write operations in a processorINTEL CORP·Filed 2015·Granted Jul 9, 2019·0 cites·18 claims
- 1936US2018181398A1Apparatus and methods of decomposing loops to improve performance and power efficiencyINTEL CORP·Filed 2016·Application pending·0 cites
- 2033US2014208074A1Instruction scheduling for a multi-strand out-of-order processorBABAYAN BORIS A·Filed 2012·Application pending·0 cites
- 2132US9811340B2Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processorKOSAREV NIKOLAY·Filed 2012·Granted Nov 7, 2017·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →