Inventor · disambiguated record
Kok Heng Choe
Also filed as: CHOE KOK HENG
20 granted patents·123 citations·filing 2004–2017
94Inventor score
Top patents by PatentIndex Score
20 records- 0192US8645450B1Multiplier-accumulator circuitry and methodsCHOE KOK HENG·Filed 2007·Granted Feb 4, 2014·34 cites·16 claims
- 0285US7164289B1Real time feedback compensation of programmable logic memoryALTERA CORP·Filed 2005·Granted Jan 16, 2007·11 cites·12 claims
- 0384US7471588B2Dual port random-access-memory circuitryALTERA CORP·Filed 2006·Granted Dec 30, 2008·13 cites·13 claims
- 0481US10536174B1Interface for efficient usage of communication circuitryINTEL CORP·Filed 2017·Granted Jan 14, 2020·3 cites·19 claims
- 0581US7542324B1FPGA equivalent input and output grid muxing on structural ASIC memoryALTERA CORP·Filed 2006·Granted Jun 2, 2009·10 cites·13 claims
- 0680US7679397B1Techniques for precision biasing output driver for a calibrated on-chip termination circuitALTERA CORP·Filed 2005·Granted Mar 16, 2010·12 cites·29 claims
- 0777US7882408B1Real time feedback compensation of programmable logic memoryALTERA CORP·Filed 2006·Granted Feb 1, 2011·7 cites·22 claims
- 0876US9543956B2Systems and methods for configuring an SOPC without a need to use an external memoryHOOI WOI JIE·Filed 2011·Granted Jan 10, 2017·5 cites·14 claims
- 0967US8261141B1Real time feedback compensation of programmable logic memoryCHOE KOK HENG·Filed 2011·Granted Sep 4, 2012·2 cites·26 claims
- 1067USRE41325EDual port random-access-memory circuitryALTERA CORP·Filed 2009·Granted May 11, 2010·5 cites·13 claims
- 1167US7319619B1Programmable logic device memory blocks with adjustable timingALTERA CORP·Filed 2006·Granted Jan 15, 2008·6 cites·20 claims
- 1262US8885392B1RAM/ROM memory circuitCHOE KOK HENG·Filed 2009·Granted Nov 11, 2014·5 cites·20 claims
- 1355US7586327B1Distributed memory circuitry on structured application-specific integrated circuit devicesALTERA CORP·Filed 2008·Granted Sep 8, 2009·2 cites·20 claims
- 1455US7071731B1Programmable Logic with Pipelined Memory OperationALTERA CORP·Filed 2005·Granted Jul 4, 2006·3 cites·20 claims
- 1553US8910102B2Configuring a programmable logic device using a configuration bit stream without phantom bitsALTERA CORP·Filed 2013·Granted Dec 9, 2014·0 cites·14 claims
- 1651US9130561B1Configuring a programmable logic device using a configuration bit stream without phantom bitsALTERA CORP·Filed 2014·Granted Sep 8, 2015·0 cites·23 claims
- 1749US9912337B2Systems and methods for configuring an SOPC without a need to use an external memoryALTERA CORP·Filed 2017·Granted Mar 6, 2018·0 cites·20 claims
- 1848US7046566B1Voltage-based timing control of memory bit linesALTERA CORP·Filed 2004·Granted May 16, 2006·5 cites·20 claims
- 1944US7901999B1FPGA equivalent input and output grid muxing on structural ASIC memoryALTERA CORP·Filed 2009·Granted Mar 8, 2011·0 cites·10 claims
- 2043US9275694B1FPGA equivalent input and output grid muxing on structural ASIC memoryCHOE KOK HENG·Filed 2011·Granted Mar 1, 2016·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →