Inventor · disambiguated record
Robert Allen Drehmel
Also filed as: DREHMEL ROBERT A · DREHMEL ROBERT ALLEN
30 granted patents·3 pending applications·1,017 citations·filing 1991–2019
97Inventor score
Top patents by PatentIndex Score
33 records- 0195US6247100B1Method and system for transmitting address commands in a multiprocessor systemIBM·Filed 2000·Granted Jun 12, 2001·120 cites·8 claims
- 0294US6526469B1Bus architecture employing varying width uni-directional command busIBM·Filed 1999·Granted Feb 25, 2003·198 cites·10 claims
- 0390US6557069B1Processor-memory bus architecture for supporting multiple processorsIBM·Filed 1999·Granted Apr 29, 2003·169 cites·15 claims
- 0490US6513091B1Data routing using status-response signalsIBM·Filed 1999·Granted Jan 28, 2003·167 cites·18 claims
- 0588US7254663B2Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modesIBM·Filed 2004·Granted Aug 7, 2007·46 cites·11 claims
- 0687US10552351B2Techniques for issuing interrupts in a data processing system with multiple scopesIBM·Filed 2019·Granted Feb 4, 2020·3 cites·20 claims
- 0787US10423550B2Managing efficient selection of a particular processor thread for handling an interruptIBM·Filed 2017·Granted Sep 24, 2019·4 cites·20 claims
- 0882US7234017B2Computer system architecture for a processor connected to a high speed bus transceiverIBM·Filed 2005·Granted Jun 19, 2007·14 cites·32 claims
- 0981US6295591B1Method of upgrading and/or servicing memory without interrupting the operation of the systemIBM·Filed 1999·Granted Sep 25, 2001·48 cites·11 claims
- 1080US7461268B2E-fuses for storing security version dataIBM·Filed 2004·Granted Dec 2, 2008·21 cites·5 claims
- 1177US7873773B2Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modesIBM·Filed 2007·Granted Jan 18, 2011·7 cites·21 claims
- 1276US6895482B1Reordering and flushing commands in a computer memory subsystemIBM·Filed 1999·Granted May 17, 2005·79 cites·8 claims
- 1372US6505306B1Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initializationIBM·Filed 1999·Granted Jan 7, 2003·31 cites·21 claims
- 1464US6628662B1Method and system for multilevel arbitration in a non-blocking crossbar switchIBM·Filed 1999·Granted Sep 30, 2003·52 cites·10 claims
- 1563US7409558B2Low-latency data decryption interfaceIBM·Filed 2004·Granted Aug 5, 2008·7 cites·6 claims
- 1662US7275125B2Pipeline bit handling circuit and method for a bus bridgeIBM·Filed 2005·Granted Sep 25, 2007·2 cites·18 claims
- 1762US6836831B2Independent sequencers in a DRAM control structureIBM·Filed 2002·Granted Dec 28, 2004·8 cites·12 claims
- 1860US10565140B2Techniques for issuing interrupts in a data processing system with multiple scopesIBM·Filed 2017·Granted Feb 18, 2020·0 cites·6 claims
- 1959US11074205B2Managing efficient selection of a particular processor thread for handling an interruptIBM·Filed 2019·Granted Jul 27, 2021·0 cites·14 claims
- 2059US10210112B2Techniques for issuing interrupts in a data processing system with multiple scopesIBM·Filed 2017·Granted Feb 19, 2019·0 cites·11 claims
- 2159US7469312B2Computer system bus bridgeIBM·Filed 2005·Granted Dec 23, 2008·1 cites·11 claims
- 2257US8069353B2Low-latency data decryption interfaceBEUKEMA BRUCE L·Filed 2008·Granted Nov 29, 2011·2 cites·5 claims
- 2353USRE44342EBus architecture employing varying width uni-directional command busDREHMEL ROBERT ALLEN·Filed 2005·Granted Jul 2, 2013·2 cites·59 claims
- 2453US7757032B2Computer system bus bridgeIBM·Filed 2008·Granted Jul 13, 2010·0 cites·9 claims
- 2553US2008175381A1E-fuses for storing security version dataIBM·Filed 2008·Application pending·0 cites
- 2649US6188627B1Method and system for improving DRAM subsystem performance using burst refresh controlIBM·Filed 1999·Granted Feb 13, 2001·11 cites·17 claims
- 2746US2006015753A1Internal RAM for integrity check valuesIBM·Filed 2004·Application pending·0 cites
- 2842US2008310622A1E-fuses for storing security version dataIBM·Filed 2008·Application pending·0 cites
- 2940US5117384AMethod and apparatus for exponent adderIBM·Filed 1991·Granted May 26, 1992·13 cites·10 claims
- 3035US6684279B1Method, apparatus, and computer program product for controlling data transferIBM·Filed 1999·Granted Jan 27, 2004·7 cites·9 claims
- 3130US6523080B1Shared bus non-sequential data ordering method and apparatusIBM·Filed 1998·Granted Feb 18, 2003·2 cites·6 claims
- 3230US6185646B1Method and apparatus for transferring data on a synchronous multi-dropIBM·Filed 1997·Granted Feb 6, 2001·2 cites·10 claims
- 3329US5748919AShared bus non-sequential data ordering method and apparatusIBM·Filed 1996·Granted May 5, 1998·1 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →