Inventor · disambiguated record
Wilhelm Haller
Also filed as: HALLER WILHELM · HALLER WILHELM E · HALLER WILHELM ERNST
34 granted patents·4 pending applications·219 citations·filing 1989–2018
97Inventor score
Top patents by PatentIndex Score
38 records- 0189US8423940B2Early noise detection and noise aware routing in circuit designDAELLENBACH LUKAS·Filed 2011·Granted Apr 16, 2013·23 cites·20 claims
- 0286US9058456B2Method and system to fix early mode slacks in a circuit designIBM·Filed 2013·Granted Jun 16, 2015·11 cites·14 claims
- 0379US8302056B2Method and system for placement of electronic circuit components in integrated circuit designGAUGLER ELMAR·Filed 2010·Granted Oct 30, 2012·8 cites·11 claims
- 0473US10031995B2Detecting circuit design flaws based on timing analysisIBM·Filed 2015·Granted Jul 24, 2018·2 cites·20 claims
- 0573US8701059B2Method and system for repartitioning a hierarchical circuit designIBM·Filed 2013·Granted Apr 15, 2014·3 cites·19 claims
- 0670US8516417B2Method and system for repartitioning a hierarchical circuit designGAUGLER ELMAR·Filed 2010·Granted Aug 20, 2013·3 cites·20 claims
- 0769US7530038B2Method and placement tool for designing the layout of an electronic circuitIBM·Filed 2006·Granted May 5, 2009·5 cites·5 claims
- 0868US7908308B2Carry-select adder structure and method to generate orthogonal signal levelsIBM·Filed 2007·Granted Mar 15, 2011·5 cites·12 claims
- 0967US9506986B2Integrated circuit chip and a method for testing the sameIBM·Filed 2014·Granted Nov 29, 2016·1 cites·16 claims
- 1064US10317465B2Integrated circuit chip and a method for testing the sameIBM·Filed 2018·Granted Jun 11, 2019·0 cites·4 claims
- 1163US7475104B2System and method for providing a double adder for decimal floating point operationsIBM·Filed 2005·Granted Jan 6, 2009·2 cites·8 claims
- 1260US10006965B2Integrated circuit chip and a method for testing the sameIBM·Filed 2016·Granted Jun 26, 2018·0 cites·17 claims
- 1359US7546565B2Method for comparing two designs of electronic circuitsIBM·Filed 2007·Granted Jun 9, 2009·2 cites·6 claims
- 1458US10528323B2Circuit for addition of multiple binary numbersIBM·Filed 2018·Granted Jan 7, 2020·0 cites·14 claims
- 1556US8612500B2Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematicHALLER WILHELM·Filed 2008·Granted Dec 17, 2013·2 cites·14 claims
- 1654US10168991B2Circuit for addition of multiple binary numbersIBM·Filed 2016·Granted Jan 1, 2019·0 cites·18 claims
- 1754US8219604B2System and method for providing a double adder for decimal floating point operationsCARLOUGH STEVEN R·Filed 2009·Granted Jul 10, 2012·0 cites·7 claims
- 1854US7095252B2Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gatesIBM·Filed 2004·Granted Aug 22, 2006·7 cites·8 claims
- 1953US6918119B2Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environmentsIBM·Filed 2001·Granted Jul 12, 2005·3 cites·16 claims
- 2053US5761521AProcessor for character strings of variable lengthIBM·Filed 1994·Granted Jun 2, 1998·27 cites·7 claims
- 2150US6836835B2Combined logic function for address limit checkingIBM·Filed 2002·Granted Dec 28, 2004·3 cites·16 claims
- 2249US7406495B2Adder structure with midcycle latch for power reductionIBM·Filed 2004·Granted Jul 29, 2008·1 cites·3 claims
- 2346US5964845AProcessing system having improved bi-directional serial clock communication circuitryIBM·Filed 1995·Granted Oct 12, 1999·18 cites·11 claims
- 2445US7224190B2Midcycle latch for power saving and switching reductionIBM·Filed 2004·Granted May 29, 2007·4 cites·6 claims
- 2544US2008071852A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 2644US2009112963A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 2743US6292819B1Binary and decimal adder unitIBM·Filed 1999·Granted Sep 18, 2001·19 cites·20 claims
- 2843US5754875AComputer system with double width data busIBM·Filed 1996·Granted May 19, 1998·19 cites·16 claims
- 2942US5138707AMethod of operating a timer in a digital data processing systemIBM·Filed 1989·Granted Aug 11, 1992·12 cites·12 claims
- 3042US2006031279A1Highly parallel structure for fast multi cycle binary and decimal adder unitIBM·Filed 2005·Application pending·0 cites
- 3140US8286115B2Fast routing of custom macrosWETTER HOLGER·Filed 2008·Granted Oct 9, 2012·0 cites·13 claims
- 3240US5928319ACombined binary/decimal adder unitIBM·Filed 1997·Granted Jul 27, 1999·13 cites·12 claims
- 3336US5634047AMethod for executing branch instructions by processing loop end conditions in a second processorIBM·Filed 1996·Granted May 27, 1997·11 cites·15 claims
- 3436US2013227250A1Simd accelerator for data comparisonHALLER WILHELM·Filed 2012·Application pending·0 cites
- 3534US8086657B2Adder structure with midcycle latch for power reductionHALLER WILHELM·Filed 2008·Granted Dec 27, 2011·0 cites·7 claims
- 3633US5944772ACombined adder and logic unitIBM·Filed 1997·Granted Aug 31, 1999·6 cites·18 claims
- 3733US5875123ACarry-select adder with pre-counting of leading zero digitsIBM·Filed 1995·Granted Feb 23, 1999·6 cites·17 claims
- 3831US5978957AVery fast pipelined shifter element with parity predictionIBM·Filed 1995·Granted Nov 2, 1999·3 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →