Inventor · disambiguated record
Robert G. Mathews
Also filed as: MATHEWS ROBERT · MATHEWS ROBERT G
9 granted patents·719 citations·filing 1997–2003
92Inventor score
Top patents by PatentIndex Score
9 records- 0196US6643831B2Method and system for extraction of parasitic interconnect impedance including inductanceSEQUENCE DESIGN INC·Filed 2002·Granted Nov 4, 2003·275 cites·28 claims
- 0293US6591407B1Method and apparatus for interconnect-driven optimization of integrated circuit designSEQUENCE DESIGN INC·Filed 2000·Granted Jul 8, 2003·146 cites·60 claims
- 0382US6291254B1Methods for determining on-chip interconnect process parametersSEQUENCE DESIGN INC·Filed 1999·Granted Sep 18, 2001·49 cites·19 claims
- 0481US6057171AMethods for determining on-chip interconnect process parametersFREQUENCY TECHNOLOGY INC·Filed 1997·Granted May 2, 2000·48 cites·6 claims
- 0580US7222311B2Method and apparatus for interconnect-driven optimization of integrated circuit designSEQUENCE DESIGN INC·Filed 2003·Granted May 22, 2007·33 cites·16 claims
- 0680US6381730B1Method and system for extraction of parasitic interconnect impedance including inductanceSEQUENCE DESIGN INC·Filed 1999·Granted Apr 30, 2002·88 cites·32 claims
- 0777US6403389B1Method for determining on-chip sheet resistivitySEQUENCE DESIGN INC·Filed 1999·Granted Jun 11, 2002·42 cites·10 claims
- 0876US6312963B1Methods for determining on-chip interconnect process parametersSEQUENCE DESIGN INC·Filed 1999·Granted Nov 6, 2001·36 cites·4 claims
- 0930US6311312B1Method for modeling a conductive semiconductor substrateSEQUENCE DESIGN INC·Filed 1999·Granted Oct 30, 2001·2 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →