Inventor · disambiguated record
Paras Mal Jain
Also filed as: MAL JAIN PARAS
3 granted patents·2 pending applications·12 citations·filing 2005–2020
59Inventor score
Technology areasG06F
Top patents by PatentIndex Score
5 records- 0176US7536662B2Method for recognizing and verifying FIFO structures in integrated circuit designsATRENTA INC·Filed 2006·Granted May 19, 2009·11 cites·17 claims
- 0261US9721057B2System and method for netlist clock domain crossing verificationSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·18 claims
- 0340US11238202B2Verifying glitches in reset path using formal verification and simulationSYNOPSYS INC·Filed 2020·Granted Feb 1, 2022·0 cites·19 claims
- 0437US2006190754A1A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit DesignATRENTA INC·Filed 2005·Application pending·0 cites
- 0528US2016342727A1Method and system for checking and correcting shoot-through in rtl simulationSYNOPSYS INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →