Inventor · disambiguated record
Satoru Mayuzumi
Also filed as: MAYUZUMI SATORU
24 granted patents·8 pending applications·146 citations·filing 1999–2023
94Inventor score
Files withSONY CORP11MAYUZUMI SATORU4NEC ELECTRONICS CORP3SANDISK TECHNOLOGIES LLC3WESTERN DIGITAL TECH INC3
Top patents by PatentIndex Score
32 records- 0196US10833101B2Three-dimensional memory device with horizontal silicon channels and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2019·Granted Nov 10, 2020·20 cites·12 claims
- 0294US10381366B1Air gap three-dimensional cross rail memory device and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Aug 13, 2019·21 cites·14 claims
- 0393US9337305B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2015·Granted May 10, 2016·6 cites·18 claims
- 0492US8896068B2Semiconductor device including source/drain regions and a gate electrode, and having contact portionsMAYUZUMI SATORU·Filed 2010·Granted Nov 25, 2014·27 cites·13 claims
- 0587US10199227B2Method for fabricating a metal high-k gate stack for a buried recessed access deviceSONY CORP·Filed 2017·Granted Feb 5, 2019·3 cites·8 claims
- 0683US10748966B2Three-dimensional memory device containing cobalt capped copper lines and method of making the sameSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Aug 18, 2020·4 cites·1 claims
- 0780US6713333B2Method for fabricating a MOSFETNEC ELECTRONICS CORP·Filed 2002·Granted Mar 30, 2004·25 cites·8 claims
- 0877US2022384652A1Semiconductor device and manufacturing method thereofSONY GROUP CORP·Filed 2022·Application pending·0 cites
- 0975US6841472B2Semiconductor device and method of fabricating the sameNEC ELECTRONICS CORP·Filed 2003·Granted Jan 11, 2005·18 cites·8 claims
- 1074US8779546B1Semiconductor memory system with bit line and method of manufacture thereofSONY CORP·Filed 2013·Granted Jul 15, 2014·3 cites·18 claims
- 1170US12087858B2Semiconductor device including stress application layerSONY GROUP CORP·Filed 2020·Granted Sep 10, 2024·0 cites·20 claims
- 1269US10854751B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2019·Granted Dec 1, 2020·0 cites·20 claims
- 1366US10535769B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2019·Granted Jan 14, 2020·0 cites·14 claims
- 1465US12469555B2Unselect word line switch bias scheme for non-volatile memory apparatusSANDISK TECHNOLOGIES INC·Filed 2023·Granted Nov 11, 2025·0 cites·17 claims
- 1563US10269961B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2018·Granted Apr 23, 2019·0 cites·13 claims
- 1661US10868177B2Semiconductor device and manufacturing method thereofSONY CORP·Filed 2018·Granted Dec 15, 2020·0 cites·32 claims
- 1760US9947790B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2017·Granted Apr 17, 2018·0 cites·19 claims
- 1859US9601622B2Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regionsSONY CORP·Filed 2016·Granted Mar 21, 2017·0 cites·20 claims
- 1958US9680007B2Method for fabricating a metal high-k gate stack for a buried recessed access deviceSONY SEMICONDUCTOR SOLUTIONS CORP·Filed 2016·Granted Jun 13, 2017·0 cites·10 claims
- 2058US2024387370A1Three-dimensional memory device containing overlying thin film transistor control circuit and method of making thereofWESTERN DIGITAL TECH INC·Filed 2023·Application pending·0 cites
- 2158US2024371760A1Three-dimensional memory device containing peripheral circuit with fin and planar field effect transistors and method of making thereofWESTERN DIGITAL TECH INC·Filed 2023·Application pending·0 cites
- 2257US8980713B2Method for fabricating a metal high-k gate stack for a buried recessed access deviceSONY CORP·Filed 2013·Granted Mar 17, 2015·0 cites·15 claims
- 2356US9337042B2Method for fabricating a metal high-k gate stack for a buried recessed access deviceSONY CORP·Filed 2015·Granted May 10, 2016·0 cites·13 claims
- 2455US2024373639A1Three-dimensional memory device containing peripheral circuit with fin field effect transistors and method of making the sameWESTERN DIGITAL TECH INC·Filed 2023·Application pending·0 cites
- 2554US9876109B2Transistors having strained channel under gate in a recessMICRON TECHNOLOGY INC·Filed 2017·Granted Jan 23, 2018·0 cites·10 claims
- 2654US9640656B2Transistors having strained channel under gate in a recessMICRON TECHNOLOGY INC·Filed 2014·Granted May 2, 2017·0 cites·25 claims
- 2753US6316836B1Semiconductor device interconnection structureNEC CORP·Filed 1999·Granted Nov 13, 2001·19 cites·6 claims
- 2852US9153663B2Semiconductor device having a stress-inducing layer between channel region and source and drain regionsMAYUZUMI SATORU·Filed 2010·Granted Oct 6, 2015·0 cites·19 claims
- 2947US2012032240A1Semiconductor device and manufacturing method thereofMAYUZUMI SATORU·Filed 2011·Application pending·0 cites
- 3038US2012199829A1Semiconductor deviceMAYUZUMI SATORU·Filed 2012·Application pending·0 cites
- 3136US2002079525A1Semiconductor device and method of fabricating the sameNEC CORP·Filed 2001·Application pending·0 cites
- 3234US2003219953A1Method for fabricating semiconductor devicesNEC ELECTRONICS CORP·Filed 2003·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →