Inventor · disambiguated record
Hui-Yin Seto
Also filed as: SETO HUI Y · SETO HUI-YIN
10 granted patents·2 pending applications·122 citations·filing 2003–2012
89Inventor score
Top patents by PatentIndex Score
12 records- 0191US7443741B2DQS strobe centering (data eye training) methodLSI CORP·Filed 2005·Granted Oct 28, 2008·31 cites·20 claims
- 0290US7525356B2Low-power, programmable multi-stage delay cellLSI CORP·Filed 2006·Granted Apr 28, 2009·30 cites·18 claims
- 0390US7215584B2Method and/or apparatus for training DQS strobe gatingLSI LOGIC CORP·Filed 2005·Granted May 8, 2007·29 cites·20 claims
- 0482US8516425B2Method and computer program for generating grounded shielding wires for signal wiringNIKITIN ANDREY·Filed 2012·Granted Aug 20, 2013·7 cites·25 claims
- 0575US7996804B2Signal delay skew reduction systemLSI CORP·Filed 2008·Granted Aug 9, 2011·6 cites·15 claims
- 0669US7605628B2System for glitch-free delay updates of a standard cell-based programmable delayLSI CORP·Filed 2007·Granted Oct 20, 2009·6 cites·20 claims
- 0768US8819354B2Feedback programmable data strobe enable architecture for DDR memory applicationsSETO HUI-YIN·Filed 2005·Granted Aug 26, 2014·6 cites·20 claims
- 0864US7394707B2Programmable data strobe enable architecture for DDR memory applicationsLSI CORP·Filed 2005·Granted Jul 1, 2008·6 cites·20 claims
- 0961US8239813B2Method and apparatus for balancing signal delay skewNIKITIN ANDREY·Filed 2011·Granted Aug 7, 2012·1 cites·17 claims
- 1041US8230143B2Memory interface architecture for maximizing access timing marginSETO HUI-YIN·Filed 2005·Granted Jul 24, 2012·0 cites·20 claims
- 1139US2005229132A1Macro cell for integrated circuit physical layer interfaceLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1228US2004260962A1Systems and methods for latching dataFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →