Inventor · disambiguated record
Norbert Bernard Eugene Lataille
Also filed as: LATAILLE NORBERT · LATAILLE NORBERT BERNARD EUGEN · LATAILLE NORBERT BERNARD EUGENE · LATAILLE NORBERT BERNARD EUGÉNE
13 granted patents·5 pending applications·179 citations·filing 2004–2014
91Inventor score
Top patents by PatentIndex Score
18 records- 0191US8271730B2Handling of write access requests to shared memory in a data processing apparatusPIRY FREDERIC CLAUDE MARIE·Filed 2007·Granted Sep 18, 2012·34 cites·13 claims
- 0287US7162590B2Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portionADVANCED RISC MACH LTD·Filed 2004·Granted Jan 9, 2007·73 cites·18 claims
- 0385US7925868B2Suppressing register renaming for conditional instructions predicted as not executedADVANCED RISC MACH LTD·Filed 2007·Granted Apr 12, 2011·18 cites·16 claims
- 0484US7590826B2Speculative data value usageADVANCED RISC MACH LTD·Filed 2006·Granted Sep 15, 2009·16 cites·19 claims
- 0583US7624253B2Determining register availability for register renamingADVANCED RISC MACH LTD·Filed 2006·Granted Nov 24, 2009·15 cites·23 claims
- 0677US7856532B2Cache logic, data processing apparatus including cache logic, and a method of operating cache logicADVANCED RISC MACH LTD·Filed 2006·Granted Dec 21, 2010·9 cites·12 claims
- 0771US9031891B2Computing system and method for controlling the execution of a decision process to maintain the data access efficiency upon receipt of an availability information inquiryAMADEUS SAS·Filed 2012·Granted May 12, 2015·2 cites·29 claims
- 0867US7809930B2Selective suppression of register renamingADVANCED RISC MACH LTD·Filed 2007·Granted Oct 5, 2010·4 cites·17 claims
- 0964US7650483B2Execution of instructions within a data processing apparatus having a plurality of processing unitsADVANCED RISC MACH LTD·Filed 2006·Granted Jan 19, 2010·3 cites·18 claims
- 1060US7698537B2Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renamingADVANCED RISC MACH LTD·Filed 2006·Granted Apr 13, 2010·2 cites·18 claims
- 1160US2016125321A1Segmented availability cacheAMADEUS SAS·Filed 2014·Application pending·0 cites
- 1257US8769251B2Data processing apparatus and method for converting data values between endian formatsLUC PHILIPPE·Filed 2006·Granted Jul 1, 2014·3 cites·13 claims
- 1346US7844800B2Method for renaming a large number of registers in a data processing system using a background channelADVANCED RISC MACH LTD·Filed 2007·Granted Nov 30, 2010·0 cites·24 claims
- 1443US2008077782A1Restoring a register renaming table within a processor following an exceptionADVANCED RISC MACH LTD·Filed 2006·Application pending·0 cites
- 1543US2008148022A1Marking registers as available for register renamingADVANCED RISC MACH LTD·Filed 2006·Application pending·0 cites
- 1642US2008077777A1Register renaming for instructions having unresolved condition codesADVANCED RISC MACH LTD·Filed 2006·Application pending·0 cites
- 1742US2005005073A1Power control within a coherent multi-processing systemADVANCED RISC MACH LTD·Filed 2004·Application pending·0 cites
- 1841US10657449B2System and method for load distribution in a networkAMADEUS SAS·Filed 2013·Granted May 19, 2020·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →