Inventor · disambiguated record
Reynold V. D'Sa
Also filed as: D SA REYNOLD V · D SA REYNOLD VIRIATO
15 granted patents·1 pending application·1,029 citations·filing 1994–2003
96Inventor score
Technology areasG06F
Files withINTEL CORP15
Top patents by PatentIndex Score
16 records- 0195US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 0291US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 0389US6374350B1System and method of maintaining and utilizing multiple return stack buffersINTEL CORP·Filed 2000·Granted Apr 16, 2002·58 cites·16 claims
- 0486US6715064B1Method and apparatus for performing sequential executions of elements in cooperation with a transformINTEL CORP·Filed 2000·Granted Mar 30, 2004·48 cites·23 claims
- 0584US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 0681US6151671ASystem and method of maintaining and utilizing multiple return stack buffersINTEL CORP·Filed 1998·Granted Nov 21, 2000·97 cites·6 claims
- 0780US6014742ATrace branch prediction unitINTEL CORP·Filed 1997·Granted Jan 11, 2000·87 cites·26 claims
- 0879US5768576AMethod and apparatus for predicting and handling resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1996·Granted Jun 16, 1998·75 cites·19 claims
- 0975US6055630ASystem and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline unitsINTEL CORP·Filed 1998·Granted Apr 25, 2000·73 cites·23 claims
- 1068US5903751AMethod and apparatus for implementing a branch target buffer in CISC processorINTEL CORP·Filed 1997·Granted May 11, 1999·38 cites·3 claims
- 1160US5944817AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1998·Granted Aug 31, 1999·27 cites·4 claims
- 1259US7334115B1Detection, recovery and prevention of bogus branchesINTEL CORP·Filed 2000·Granted Feb 19, 2008·8 cites·25 claims
- 1355US5918046AMethod and apparatus for a branch instruction pointer tableINTEL CORP·Filed 1997·Granted Jun 29, 1999·30 cites·20 claims
- 1455US5706492AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1996·Granted Jan 6, 1998·22 cites·19 claims
- 1545US6493821B1Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information tableINTEL CORP·Filed 1998·Granted Dec 10, 2002·17 cites·33 claims
- 1644US2004088525A1Method and apparatus for performing sequential executions of elements in cooperation with a transformFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →