Inventor · disambiguated record
Xinyuan Dou
Also filed as: DOU XINYUAN
15 granted patents·1 pending application·66 citations·filing 2015–2024
90Inventor score
Top patents by PatentIndex Score
16 records- 0195US10090382B1Integrated circuit structure including single diffusion break and end isolation region, and methods of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 2, 2018·14 cites·20 claims
- 0295US10014296B1Fin-type field effect transistors with single-diffusion breaks and methodGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 3, 2018·19 cites·20 claims
- 0392US10074732B1Methods of forming short channel and long channel finFET devices so as to adjust threshold voltagesGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 11, 2018·11 cites·14 claims
- 0487US10522679B2Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 31, 2019·6 cites·20 claims
- 0587US10083873B1Semiconductor structure with uniform gate heightsGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 25, 2018·5 cites·10 claims
- 0686US10043713B1Method to reduce FinFET short channel gate heightGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 7, 2018·4 cites·9 claims
- 0780US10580857B2Method to form high performance fin profile for 12LP and aboveGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·19 claims
- 0877US9831098B2Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealingGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 28, 2017·3 cites·20 claims
- 0970US10818557B2Integrated circuit structure to reduce soft-fail incidence and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 27, 2020·1 cites·19 claims
- 1058US10643900B2Method to reduce FinFET short channel gate heightGLOBALFOUNDRIES INC·Filed 2018·Granted May 5, 2020·0 cites·20 claims
- 1157US2025098235A1Semiconductor device and method for manufacturing sameMICROCHIP TECH INC·Filed 2024·Application pending·0 cites
- 1253US11164954B2Gate capping layers of semiconductor devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Nov 2, 2021·0 cites·20 claims
- 1351US10714380B2Method of forming smooth sidewall structures using spacer materialsGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·20 claims
- 1445US10910276B1STI structure with liner along lower portion of longitudinal sides of active region, and related FET and methodGLOBALFOUNDRIES INC·Filed 2019·Granted Feb 2, 2021·0 cites·20 claims
- 1545US10347531B2Middle of the line (MOL) contact formation method and structureGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
- 1642US10153211B1Methods, apparatus, and system for fabricating finFET devices with increased breakdown voltageGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 11, 2018·0 cites·20 claims
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