Inventor · disambiguated record
Sireesha Gogineni
Also filed as: GOGINENI SIREESHA
7 granted patents·3 pending applications·20 citations·filing 2015–2022
74Inventor score
Technology areasH10W
Top patents by PatentIndex Score
10 records- 0194US9871007B2Packaged integrated circuit device with cantilever structureINTEL CORP·Filed 2015·Granted Jan 16, 2018·20 cites·9 claims
- 0270US12046581B2Integrated circuit package with glass spacerINTEL CORP·Filed 2022·Granted Jul 23, 2024·0 cites·20 claims
- 0352US11393788B2Integrated circuit package with glass spacerINTEL CORP·Filed 2016·Granted Jul 19, 2022·0 cites·12 claims
- 0450US11848292B2Pad design for thermal fatigue resistance and interconnect joint reliabilityINTEL CORP·Filed 2018·Granted Dec 19, 2023·0 cites·25 claims
- 0550US10490516B2Packaged integrated circuit device with cantilever structureINTEL CORP·Filed 2018·Granted Nov 26, 2019·0 cites·5 claims
- 0648US11694976B2Bowl shaped padINTEL CORP·Filed 2018·Granted Jul 4, 2023·0 cites·16 claims
- 0733US2018190776A1Semiconductor chip package with cavityGOGINENI SIREESHA·Filed 2016·Application pending·0 cites
- 0832US11881441B2Stacked die semiconductor package spacer dieINTEL CORP·Filed 2017·Granted Jan 23, 2024·0 cites·9 claims
- 0931US2018323172A1Eliminating die shadow effects by dummy die beams for solder joint reliability improvementINTEL CORP·Filed 2015·Application pending·0 cites
- 1027US2017186701A1Crack resistant electronic device package substratesINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →