Inventor
TEH WENG HONG
US47 patents
⚠️ This page may combine multiple inventors who share the name “TEH WENG HONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS9190380B2Nov 17, 2015
High density substrate routing in BBUL package
INTEL CORP64 citations99
US9171816B2Oct 27, 2015
High density substrate routing in BBUL package
INTEL CORP53 citations98
US9153552B2Oct 6, 2015
Bumpless build-up layer package including an integrated heat spreader
INTEL CORP43 citations97
US8912670B2Dec 16, 2014
Bumpless build-up layer package including an integrated heat spreader
INTEL CORP53 citations97
US9437569B2Sep 6, 2016
High density substrate routing in BBUL package
INTEL CORP23 citations96
US10199346B2Feb 5, 2019
High density substrate routing in package
INTEL CORP12 citations93
US9929119B2Mar 27, 2018
High density substrate routing in BBUL package
INTEL CORP11 citations93
US9368401B2Jun 14, 2016
Embedded structures for package-on-package architecture
INTEL CORP13 citations91
US9520376B2Dec 13, 2016
Bumpless build-up layer package including an integrated heat spreader
INTEL CORP11 citations83
US8866287B2Oct 21, 2014
Embedded structures for package-on-package architecture
INTEL CORP11 citations82
US10636769B2Apr 28, 2020
Semiconductor package having spacer layer
INTEL CORP2 citations73
US9686870B2Jun 20, 2017
Method of forming a microelectronic device package
INTEL CORP2 citations73
US9345184B2May 17, 2016
Magnetic field shielding for packaging build-up architectures
INTEL CORP6 citations72
US9748177B2Aug 29, 2017
Embedded structures for package-on-package architecture
INTEL CORP4 citations71
US12327807B2Jun 10, 2025
High density substrate routing in package
INTEL CORP0 citations63
US12051667B2Jul 30, 2024
High density substrate routing in package
INTEL CORP0 citations63
US11810884B2Nov 7, 2023
High density substrate routing in package
INTEL CORP0 citations63
US11251150B2Feb 15, 2022
High density substrate routing in package
INTEL CORP0 citations63
US9275969B2Mar 1, 2016
Optical interconnect on bumpless build-up layer package
INTEL CORP2 citations63
US11201128B2Dec 14, 2021
Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
INTEL CORP0 citations62
US9242854B2Jan 26, 2016
Hermetic encapsulation for microelectromechanical systems (MEMS) devices
INTEL CORP2 citations61
US10861815B2Dec 8, 2020
High density substrate routing in package
INTEL CORP0 citations52
US10508961B2Dec 17, 2019
Semiconductor package with air pressure sensor
INTEL CORP0 citations52
US10438915B2Oct 8, 2019
High density substrate routing in package
INTEL CORP0 citations52
US10156583B2Dec 18, 2018
Method of making an accelerometer
INTEL CORP0 citations52
US10083936B2Sep 25, 2018
Semiconductor package having spacer layer
INTEL CORP0 citations52
US9800015B2Oct 24, 2017
Optical interconnect on bumpless build-up layer package
INTEL CORP1 citations52
US9674945B2Jun 6, 2017
Heterogeneous integration of microfluidic devices in package structures
INTEL CORP0 citations52
US9576909B2Feb 21, 2017
Bumpless die-package interface for bumpless build-up layer (BBUL)
INTEL CORP1 citations52
US10179729B2Jan 15, 2019
Hermetic encapsulation for microelectromechanical systems (MEMS) devices
INTEL CORP0 citations50
TEH WENG HONG
9 patentsUS8633551B1Jan 21, 2014
Semiconductor package with mechanical fuse
TEH WENG HONG30 citations92
US9490196B2Nov 8, 2016
Multi die package having a die and a spacer layer in a recess
TEH WENG HONG4 citations84
US8937382B2Jan 20, 2015
Secondary device integration into coreless microelectronic device packages
TEH WENG HONG8 citations84
US9520350B2Dec 13, 2016
Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
TEH WENG HONG5 citations71
US9601421B2Mar 21, 2017
BBUL material integration in-plane with embedded die for warpage control
TEH WENG HONG3 citations70
US9299660B2Mar 29, 2016
Controlled solder-on-die integrations on packages and methods of assembling same
TEH WENG HONG0 citations52
US9505610B2Nov 29, 2016
Device, system and method for providing MEMS structures of a semiconductor package
TEH WENG HONG0 citations45
US9162867B2Oct 20, 2015
Through-silicon via resonators in chip packages and methods of assembling same
TEH WENG HONG0 citations42
US9708178B2Jul 18, 2017
Integration of laminate MEMS in BBUL coreless package
TEH WENG HONG0 citations41
WESTERN DIGITAL TECH INC
3 patentsUS11264301B2Mar 1, 2022
System and method to enhance reliability in connection with arrangements including circuits
WESTERN DIGITAL TECH INC0 citations55
US11094604B2Aug 17, 2021
System and method to enhance solder joint reliability
WESTERN DIGITAL TECH INC0 citations55
US10636722B2Apr 28, 2020
System and method to enhance solder joint reliability
WESTERN DIGITAL TECH INC0 citations45