Inventor · disambiguated record
Maxim Loktyukhin
Also filed as: LOKTYUKHIN MAXIM
19 granted patents·2 pending applications·47 citations·filing 2009–2023
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0186US11106461B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2018·Granted Aug 31, 2021·2 cites·24 claims
- 0286US9886277B2Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sourcesINTEL CORP·Filed 2013·Granted Feb 6, 2018·9 cites·23 claims
- 0384US9940131B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·28 claims
- 0484US9940130B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·22 claims
- 0584US9916160B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Mar 13, 2018·4 cites·20 claims
- 0681US9164762B2Rotate instructions that complete execution without reading carry flagINTEL CORP·Filed 2013·Granted Oct 20, 2015·4 cites·31 claims
- 0779US10296347B2Fusible instructions and logic to provide or-test and and-test functionality using multiple test sourcesINTEL CORP·Filed 2016·Granted May 21, 2019·2 cites·20 claims
- 0879US9483266B2Fusible instructions and logic to provide OR-test and AND-test functionality using multiple test sourcesLOKTYUKHIN MAXIM·Filed 2013·Granted Nov 1, 2016·5 cites·16 claims
- 0977US8549264B2Add instructions to add three source operandsGOPAL VINODH·Filed 2009·Granted Oct 1, 2013·6 cites·30 claims
- 1077US8504807B2Rotate instructions that complete execution without reading carry flagGOPAL VINODH·Filed 2009·Granted Aug 6, 2013·4 cites·22 claims
- 1175US11900108B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2021·Granted Feb 13, 2024·0 cites·19 claims
- 1262US10656947B2Processor to perform a bit range isolation instructionINTEL CORP·Filed 2018·Granted May 19, 2020·0 cites·13 claims
- 1361US9804852B2Conditional execution support for ISA instructions using prefixesCOMBS JONATHAN D·Filed 2011·Granted Oct 31, 2017·1 cites·18 claims
- 1460US10579380B2System-on-chip (SoC) to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·15 claims
- 1560US10579379B2Processor to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Mar 3, 2020·0 cites·15 claims
- 1660US10372455B2Hand held device to perform a bit range isolation instructionINTEL CORP·Filed 2014·Granted Aug 6, 2019·0 cites·19 claims
- 1760US9990201B2Multiplication instruction for which execution completes without writing a carry flagGOPAL VINODH·Filed 2009·Granted Jun 5, 2018·1 cites·32 claims
- 1859US10649774B2Multiplication instruction for which execution completes without writing a carry flagINTEL CORP·Filed 2017·Granted May 12, 2020·0 cites·23 claims
- 1958US9003170B2Bit range isolation instructions, methods, and apparatusLOKTYUKHIN MAXIM·Filed 2009·Granted Apr 7, 2015·1 cites·12 claims
- 2050US2024103865A1Vector multiply-add/subtract with intermediate roundingESPIG MICHAEL·Filed 2023·Application pending·0 cites
- 2141US2014108480A1Apparatus and method for vector compute and accumulateOULD-AHMED-VALL ELMOUSTAPHA·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →