Inventor · disambiguated record
Yih-Shung Lin
Also filed as: LIN YIH S · LIN YIH-SHUNG
42 granted patents·2 pending applications·1,006 citations·filing 1986–2006
98Inventor score
Files withSGS THOMSON MICROELECTRONICS14ST MICROELECTRONICS INC12TAIWAN SEMICONDUCTOR MFG8CHARTERED SEMICONDUCTOR MFG7INTEL CORP2
Top patents by PatentIndex Score
44 records- 0195US7176137B2Method for multiple spacer width controlTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 13, 2007·101 cites·20 claims
- 0291US5514908AIntegrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundariesSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 7, 1996·88 cites·9 claims
- 0390US5435888AEnhanced planarization technique for an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Jul 25, 1995·88 cites·21 claims
- 0486US5108951AMethod for forming a metal contactSGS THOMSON MICROELECTRONICS·Filed 1990·Granted Apr 28, 1992·80 cites·19 claims
- 0583US6943077B2Selective spacer layer deposition method for forming spacers with different widthsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 13, 2005·24 cites·21 claims
- 0683US5652464AIntegrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundariesSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jul 29, 1997·43 cites·13 claims
- 0783US4755480AMethod of making a silicon nitride resistor using plasma enhanced chemical vapor depositionINTEL CORP·Filed 1986·Granted Jul 5, 1988·46 cites·3 claims
- 0879US7118451B2CMP apparatus and process sequence methodTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Oct 10, 2006·20 cites·20 claims
- 0979US5658828AMethod for forming an aluminum contact through an insulating layerSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 19, 1997·49 cites·18 claims
- 1075US5841195ASemiconductor contact via structureST MICROELECTRONICS INC·Filed 1995·Granted Nov 24, 1998·45 cites·24 claims
- 1175US4786612APlasma enhanced chemical vapor deposited vertical silicon nitride resistorINTEL CORP·Filed 1987·Granted Nov 22, 1988·31 cites·11 claims
- 1273US6746900B1Method for forming a semiconductor device having high-K gate dielectric materialTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jun 8, 2004·17 cites·25 claims
- 1372US6207554B1Gap filling process in integrated circuits using low dielectric constant materialsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Mar 27, 2001·39 cites·22 claims
- 1471USRE39690EEnhanced planarization technique for an integrated circuitST MICROELECTRONICS INC·Filed 2001·Granted Jun 12, 2007·9 cites·29 claims
- 1570US7294043B2CMP apparatus and process sequence methodTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Nov 13, 2007·4 cites·11 claims
- 1666US7004814B2CMP process control methodTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Feb 28, 2006·11 cites·23 claims
- 1765US6183189B1Self aligning wafer chuck design for wafer processing toolsCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Feb 6, 2001·35 cites·21 claims
- 1864US5837613AEnhanced planarization technique for an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Nov 17, 1998·19 cites·21 claims
- 1963US7271103B2Surface treated low-k dielectric as diffusion barrier for copper metallizationTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 18, 2007·8 cites·12 claims
- 2061US6191033B1Method of fabricating an integrated circuit with improved contact barrierST MICROELECTRONICS INC·Filed 1997·Granted Feb 20, 2001·15 cites·4 claims
- 2158US4978637ALocal interconnect process for integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1989·Granted Dec 18, 1990·20 cites·9 claims
- 2257US5943598AIntegrated circuit with planarized dielectric layer between successive polysilicon layersST MICROELECTRONICS INC·Filed 1995·Granted Aug 24, 1999·23 cites·19 claims
- 2356US6127238APlasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier layer for high density plasma chemical vapor deposited (HDP-CVD) dielectric layerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 3, 2000·21 cites·9 claims
- 2456US5986330AEnhanced planarization technique for an integrated circuitST MICROELECTRONICS INC·Filed 1998·Granted Nov 16, 1999·13 cites·22 claims
- 2556US5246883ASemiconductor contact via structure and methodSGS THOMSON MICROELECTRONICS·Filed 1992·Granted Sep 21, 1993·22 cites·15 claims
- 2654US5485035AMethod for planarization of an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Jan 16, 1996·23 cites·9 claims
- 2753US4933304AMethod for reducing the surface reflectance of a metal layer during semiconductor processingSGS THOMSON MICROELECTRONICS·Filed 1988·Granted Jun 12, 1990·18 cites·10 claims
- 2849US5976969AMethod for forming an aluminum contactST MICROELECTRONICS INC·Filed 1997·Granted Nov 2, 1999·11 cites·7 claims
- 2948US6291344B1Integrated circuit with improved contact barrierST MICROELECTRONICS INC·Filed 2000·Granted Sep 18, 2001·3 cites·6 claims
- 3048US5597983AProcess of removing polymers in semiconductor viasSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jan 28, 1997·14 cites·5 claims
- 3148US2006113616A1Selective spacer layer deposition method for forming spacers with different widthsLIU AI-SEN·Filed 2005·Application pending·0 cites
- 3245US5918152AGap filling method using high pressureCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jun 29, 1999·13 cites·16 claims
- 3342US6558739B1Titanium nitride/titanium tungsten alloy composite barrier layer for integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted May 6, 2003·11 cites·12 claims
- 3439US6617242B1Method for fabricating interlevel contacts of aluminum/refractory metal alloysST MICROELECTRONICS INC·Filed 1995·Granted Sep 9, 2003·6 cites·19 claims
- 3539US6054390AGrazing incident angle processing method for microelectronics layer fabricationCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Apr 25, 2000·9 cites·11 claims
- 3638US6242811B1Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperatureST MICROELECTRONICS INC·Filed 1998·Granted Jun 5, 2001·5 cites·11 claims
- 3738US2001012687A1Gap filling process in integrated circuits using low dielectric constant materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Application pending·0 cites
- 3837US5412868AProcess of removing polymers in semiconductor viasSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 9, 1995·8 cites·8 claims
- 3936US5930673AMethod for forming a metal contactST MICROELECTRONICS INC·Filed 1995·Granted Jul 27, 1999·4 cites·39 claims
- 4035US7011929B2Method for forming multiple spacer widthsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Mar 14, 2006·0 cites·20 claims
- 4135US6433435B2Aluminum contact structure for integrated circuitsST MICROELECTRONICS INC·Filed 1998·Granted Aug 13, 2002·3 cites·20 claims
- 4233USRE35111ELocal interconnect process for integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1992·Granted Dec 5, 1995·4 cites·11 claims
- 4332US5633534AIntegrated circuit with enhanced planarizationSGS THOMSON MICROELECTRONICS·Filed 1996·Granted May 27, 1997·1 cites·24 claims
- 4430US5075761ALocal interconnect for integrated circuitsSGS THOMSON MICROELECTRONICS·Filed 1990·Granted Dec 24, 1991·2 cites·8 claims
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