Inventor · disambiguated record
Satish R. Ganesan
Also filed as: GANESAN SATISH R
11 granted patents·154 citations·filing 2002–2007
91Inventor score
Technology areasG06F
Files withXILINX INC11
Top patents by PatentIndex Score
11 records- 0190US7721090B1Event-driven simulation of IP using third party event-driven simulatorsXILINX INC·Filed 2006·Granted May 18, 2010·28 cites·19 claims
- 0285US7426709B1Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded systemXILINX INC·Filed 2005·Granted Sep 16, 2008·16 cites·16 claims
- 0377US7606694B1Framework for cycle accurate simulationXILINX INC·Filed 2006·Granted Oct 20, 2009·9 cites·20 claims
- 0476US7676661B1Method and system for function acceleration using custom instructionsXILINX INC·Filed 2004·Granted Mar 9, 2010·24 cites·5 claims
- 0573US7243330B1Method and apparatus for providing self-implementing hardware-software librariesXILINX INC·Filed 2005·Granted Jul 10, 2007·8 cites·15 claims
- 0671US7111273B1Softpal implementation and mapping technology for FPGAs with dedicated resourcesXILINX INC·Filed 2003·Granted Sep 19, 2006·16 cites·43 claims
- 0771US6833730B1PLD configurable logic block enabling the rapid calculation of sum-of-products functionsXILINX INC·Filed 2002·Granted Dec 21, 2004·17 cites·29 claims
- 0866US7840781B1Circuit arrangement for profiling a programmable processor connected via a uni-directional busXILINX INC·Filed 2007·Granted Nov 23, 2010·4 cites·15 claims
- 0966US7310594B1Method and system for designing a multiprocessorXILINX INC·Filed 2002·Granted Dec 18, 2007·13 cites·24 claims
- 1065US7340585B1Method and system for fast linked processor in a system on a chip (SoC)XILINX INC·Filed 2002·Granted Mar 4, 2008·12 cites·19 claims
- 1158US7131091B1Generating fast logic simulation models for a PLD design descriptionXILINX INC·Filed 2004·Granted Oct 31, 2006·7 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →