Inventor · disambiguated record
Piyush Sagdeo
Also filed as: SAGDEO PIYUSH · SAGDEO PIYUSH GIRISH
11 granted patents·70 citations·filing 2013–2023
87Inventor score
Files withWESTERN DIGITAL TECH INC7BHALERAO ABHIJEET1KOCHAR MRINAL1SANDISK TECHNOLOGIES INC1SANDISK TECHNOLOGIES LLC1
Top patents by PatentIndex Score
11 records- 0196US10235294B1Pre-read voltage pulse for first read error handlingSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Mar 19, 2019·36 cites·20 claims
- 0288US10734079B1Sub block mode read scrub design for non-volatile memoryWESTERN DIGITAL TECH INC·Filed 2019·Granted Aug 4, 2020·9 cites·20 claims
- 0384US10790031B1System handling for first read read disturbWESTERN DIGITAL TECH INC·Filed 2019·Granted Sep 29, 2020·4 cites·20 claims
- 0480US10691372B1Transistor threshold voltage maintenance in 3D memoryWESTERN DIGITAL TECH INC·Filed 2018·Granted Jun 23, 2020·5 cites·20 claims
- 0579US9235470B2Adaptive EPWR (enhanced post write read) schedulingBHALERAO ABHIJEET·Filed 2013·Granted Jan 12, 2016·8 cites·20 claims
- 0677US9804922B2Partial bad block detection and re-use using EPWR for block based architecturesSANDISK TECHNOLOGIES INC·Filed 2014·Granted Oct 31, 2017·5 cites·19 claims
- 0762US9195587B2Enhanced dynamic read process with single-level cell segmentationKOCHAR MRINAL·Filed 2013·Granted Nov 24, 2015·3 cites·20 claims
- 0861US12360850B2System recovery during CGI-WL defectWESTERN DIGITAL TECH INC·Filed 2023·Granted Jul 15, 2025·0 cites·20 claims
- 0958US11704190B2UECC failure handling methodWESTERN DIGITAL TECH INC·Filed 2021·Granted Jul 18, 2023·0 cites·20 claims
- 1045US10936415B2Error correction scheme in flash memoryWESTERN DIGITAL TECH INC·Filed 2019·Granted Mar 2, 2021·0 cites·12 claims
- 1139US11984181B2Systems and methods for evaluating integrity of adjacent sub blocks of data storage apparatusesWESTERN DIGITAL TECH INC·Filed 2019·Granted May 14, 2024·0 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →