Inventor · disambiguated record
Gregory Salyer
Also filed as: SALYER GREGORY
12 granted patents·2 pending applications·400 citations·filing 1983–2003
93Inventor score
Files withIBM13
Top patents by PatentIndex Score
14 records- 0184US5265232ACoherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the dataIBM·Filed 1991·Granted Nov 23, 1993·121 cites·46 claims
- 0266US7552232B2Speculative method and system for rapid data communicationsIBM·Filed 2003·Granted Jun 23, 2009·13 cites·19 claims
- 0366US5455831AFrame group transmission and reception for parallel/serial busesIBM·Filed 1993·Granted Oct 3, 1995·50 cites·23 claims
- 0462US5357608AConfigurable, recoverable parallel busIBM·Filed 1992·Granted Oct 18, 1994·42 cites·33 claims
- 0560US5509122AConfigurable, recoverable parallel busIBM·Filed 1993·Granted Apr 16, 1996·34 cites·5 claims
- 0659US5412803ACommunications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transferIBM·Filed 1992·Granted May 2, 1995·35 cites·22 claims
- 0754US5267240AFrame-group transmission and reception for parallel/serial busesIBM·Filed 1992·Granted Nov 30, 1993·19 cites·23 claims
- 0851US5548623ANull words for pacing serial links to driver and receiver speedsIBM·Filed 1993·Granted Aug 20, 1996·22 cites·7 claims
- 0951US5455830AError detection and recovery in parallel/serial busesFiled 1993·Granted Oct 3, 1995·23 cites·18 claims
- 1047US4635186ADetection and correction of multi-chip synchronization errorsIBM·Filed 1983·Granted Jan 6, 1987·16 cites·10 claims
- 1145US2005081080A1Error recovery for data processing systems transferring message packets through communications adaptersIBM·Filed 2003·Application pending·0 cites
- 1244US5418939AConcurrent maintenance of degraded parallel/serial busesIBM·Filed 1993·Granted May 23, 1995·15 cites·10 claims
- 1341US2005080869A1Transferring message packets from a first node to a plurality of nodes in broadcast fashion via direct memory to memory transferIBM·Filed 2003·Application pending·0 cites
- 1438US5680575AInterconnect failure detection and cache reset apparatusIBM·Filed 1995·Granted Oct 21, 1997·10 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →