Inventor · disambiguated record
Paul M. Solomon
Also filed as: SOLOMON PAUL · SOLOMON PAUL M · SOLOMON PAUL MICHAEL
136 granted patents·12 pending applications·3,413 citations·filing 1981–2024
99Inventor score
Top patents by PatentIndex Score
148 records- 0199US7446025B2Method of forming vertical FET with nanowire channels and a silicided bottom contactIBM·Filed 2007·Granted Nov 4, 2008·155 cites·1 claims
- 0298US9852790B1Circuit methodology for highly linear and symmetric resistive processing unitIBM·Filed 2016·Granted Dec 26, 2017·59 cites·20 claims
- 0398US7459752B2Ultra thin body fully-depleted SOI MOSFETsIBM·Filed 2006·Granted Dec 2, 2008·283 cites·18 claims
- 0498US7230286B2Vertical FET with nanowire channels and a silicided bottom contactIBM·Filed 2005·Granted Jun 12, 2007·109 cites·13 claims
- 0598US6057212AMethod for making bonded metal back-plane substratesIBM·Filed 1998·Granted May 2, 2000·388 cites·26 claims
- 0698US5471948AMethod of making a compound semiconductor having metallic inclusionsIBM·Filed 1994·Granted Dec 5, 1995·242 cites·6 claims
- 0798US5371399ACompound semiconductor having metallic inclusions and devices fabricated therefromIBM·Filed 1993·Granted Dec 6, 1994·237 cites·41 claims
- 0897US7253431B2Method and apparatus for solution processed doping of carbon nanotubeIBM·Filed 2005·Granted Aug 7, 2007·90 cites·27 claims
- 0997US5886376AEEPROM having coplanar on-insulator FET and control gateIBM·Filed 1996·Granted Mar 23, 1999·251 cites·23 claims
- 1096US5960265AMethod of making EEPROM having coplanar on-insulator FET and control gateIBM·Filed 1997·Granted Sep 28, 1999·163 cites·7 claims
- 1196US5773331AMethod for making single and double gate field effect transistors with sidewall source-drain contactsIBM·Filed 1996·Granted Jun 30, 1998·192 cites·10 claims
- 1295US7749905B2Vertical Fet with nanowire channels and a silicided bottom contactIBM·Filed 2008·Granted Jul 6, 2010·23 cites·12 claims
- 1395US5019882AGermanium channel silicon MOSFETIBM·Filed 1989·Granted May 28, 1991·108 cites·15 claims
- 1494US10269425B2Circuit methodology for highly linear and symmetric resistive processing unitIBM·Filed 2017·Granted Apr 23, 2019·13 cites·20 claims
- 1594US10134472B1Floating gate architecture for deep neural network applicationIBM·Filed 2017·Granted Nov 20, 2018·16 cites·20 claims
- 1694US8258031B2Fabrication of a vertical heterojunction tunnel-FETLAUER ISAAC·Filed 2010·Granted Sep 4, 2012·19 cites·16 claims
- 1794US6580132B1Damascene double-gate FETIBM·Filed 2002·Granted Jun 17, 2003·76 cites·10 claims
- 1893US7999251B2Nanowire MOSFET with doped epitaxial contacts for source and drainIBM·Filed 2006·Granted Aug 16, 2011·22 cites·15 claims
- 1993US6645861B2Self-aligned silicide process for silicon sidewall source and drain contactsIBM·Filed 2001·Granted Nov 11, 2003·71 cites·35 claims
- 2092US8741756B2Contacts-first self-aligned carbon nanotube transistor with gate-all-aroundFRANKLIN AARON D·Filed 2012·Granted Jun 3, 2014·14 cites·20 claims
- 2192US8674412B2Contacts-first self-aligned carbon nanotube transistor with gate-all-aroundFRANKLIN AARON D·Filed 2012·Granted Mar 18, 2014·14 cites·20 claims
- 2292US6555880B2Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed therebyIBM·Filed 2001·Granted Apr 29, 2003·54 cites·9 claims
- 2391US10332874B2Indirect readout FETIBM·Filed 2017·Granted Jun 25, 2019·6 cites·12 claims
- 2491US10204907B2Metal-insulator-metal capacitor analog memory unit cellIBM·Filed 2018·Granted Feb 12, 2019·6 cites·20 claims
- 2591US8785995B2Ferroelectric semiconductor transistor devices having gate modulated conductive layerDUBOURDIEU CATHERINE A·Filed 2011·Granted Jul 22, 2014·17 cites·23 claims
- 2691US8614436B2Solid state klystronSOLOMON PAUL M·Filed 2012·Granted Dec 24, 2013·10 cites·16 claims
- 2791US8455311B2Solid state klystronSOLOMON PAUL M·Filed 2012·Granted Jun 4, 2013·10 cites·17 claims
- 2890US11101219B2Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elementsIBM·Filed 2019·Granted Aug 24, 2021·3 cites·18 claims
- 2990US10319439B1Resistive processing unit weight reading via collection of differential current from first and second memory elementsIBM·Filed 2018·Granted Jun 11, 2019·10 cites·20 claims
- 3090US10269714B2Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elementsIBM·Filed 2016·Granted Apr 23, 2019·4 cites·9 claims
- 3190US6339002B1Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contactsIBM·Filed 2000·Granted Jan 15, 2002·51 cites·22 claims
- 3289US10985105B2Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elementsIBM·Filed 2018·Granted Apr 20, 2021·3 cites·18 claims
- 3389US10468432B1BEOL cross-bar array ferroelectric synapse units for domain wall movementIBM·Filed 2018·Granted Nov 5, 2019·7 cites·20 claims
- 3489US10374041B2Field effect transistor with controllable resistanceIBM·Filed 2017·Granted Aug 6, 2019·4 cites·7 claims
- 3589US10079234B1Metal-insulator-metal capacitor analog memory unit cellIBM·Filed 2017·Granted Sep 18, 2018·5 cites·11 claims
- 3689US6444578B1Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devicesIBM·Filed 2001·Granted Sep 3, 2002·50 cites·50 claims
- 3789US6437422B1Active devices using threadsIBM·Filed 2001·Granted Aug 20, 2002·46 cites·61 claims
- 3889US5506520AEnergy conserving clock pulse generating circuitsIBM·Filed 1995·Granted Apr 9, 1996·61 cites·14 claims
- 3988US7259049B2Self-aligned isolation double-gate FETIBM·Filed 2005·Granted Aug 21, 2007·11 cites·12 claims
- 4087US8283703B2Solid state KlystronSOLOMON PAUL M·Filed 2007·Granted Oct 9, 2012·10 cites·16 claims
- 4186US6864520B2Germanium field effect transistor and method of fabricating the sameIBM·Filed 2002·Granted Mar 8, 2005·46 cites·20 claims
- 4286US4483726ADouble self-aligned fabrication process for making a bipolar transistor structure having a small polysilicon-to-extrinsic base contact areaIBM·Filed 1983·Granted Nov 20, 1984·69 cites·6 claims
- 4385US9472368B2Piezoelectronic switch device for RF applicationsIBM·Filed 2014·Granted Oct 18, 2016·4 cites·16 claims
- 4485US7091069B2Ultra thin body fully-depleted SOI MOSFETsIBM·Filed 2004·Granted Aug 15, 2006·32 cites·13 claims
- 4585US6946696B2Self-aligned isolation double-gate FETIBM·Filed 2002·Granted Sep 20, 2005·29 cites·18 claims
- 4684US10586849B2Field effect transistor with controllable resistanceIBM·Filed 2019·Granted Mar 10, 2020·2 cites·3 claims
- 4784US9915561B1Self-clocked low noise photoreceiver (SCLNP)IBM·Filed 2016·Granted Mar 13, 2018·3 cites·20 claims
- 4884US6333247B1Two-step MOSFET gate formation for high-density devicesIBM·Filed 2000·Granted Dec 25, 2001·33 cites·19 claims
- 4983US10411101B1P-N junction based devices with single species impurity for P-type and N-type dopingIBM·Filed 2018·Granted Sep 10, 2019·2 cites·9 claims
- 5083US8796735B2Fabrication of a vertical heterojunction tunnel-FETLAUER ISAAC·Filed 2012·Granted Aug 5, 2014·6 cites·11 claims
Showing the top 50 of 148 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →