Inventor · disambiguated record
Frank O'Mahony
Also filed as: O'MAHONY FRANK · O'MAHONY FRANK P · O'MAHONY FRANK PATRICK
27 granted patents·6 pending applications·130 citations·filing 2001–2025
95Inventor score
Top patents by PatentIndex Score
33 records- 0195US9596037B2Apparatus and method for measuring power supply noiseINTEL CORP·Filed 2015·Granted Mar 14, 2017·10 cites·21 claims
- 0290US9998125B2Clock calibration using asynchronous digital samplingINTEL CORP·Filed 2013·Granted Jun 12, 2018·14 cites·22 claims
- 0388US11722128B2Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)INTEL CORP·Filed 2021·Granted Aug 8, 2023·2 cites·20 claims
- 0487US9116204B2On-die all-digital delay measurement circuitO'MAHONY FRANK·Filed 2012·Granted Aug 25, 2015·8 cites·23 claims
- 0587US7710210B2Apparatus for distributing a signalINTEL CORP·Filed 2007·Granted May 4, 2010·16 cites·8 claims
- 0683US11070200B2Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)INTEL CORP·Filed 2018·Granted Jul 20, 2021·4 cites·25 claims
- 0781US10079648B2Apparatus and method for measuring power supply noiseINTEL CORP·Filed 2017·Granted Sep 18, 2018·3 cites·21 claims
- 0878US12294003B2Integrated circuit structures including backside viasINTEL CORP·Filed 2023·Granted May 6, 2025·0 cites·16 claims
- 0978US7697601B2Equalizers and offset controlINTEL CORP·Filed 2005·Granted Apr 13, 2010·10 cites·16 claims
- 1078US2025228012A1Integrated circuit structures including backside viasINTEL CORP·Filed 2025·Application pending·0 cites
- 1177US6909127B2Low loss interconnect structure for use in microelectronic circuitsINTEL CORP·Filed 2001·Granted Jun 21, 2005·21 cites·28 claims
- 1276US7683729B2Injection locked LC VCO clock deskewingINTEL CORP·Filed 2007·Granted Mar 23, 2010·7 cites·18 claims
- 1375US12111786B2Active inductor based high-bandwidth 2-state 4-way data serialization apparatus and methodINTEL CORP·Filed 2021·Granted Oct 8, 2024·1 cites·19 claims
- 1474US7352059B2Low loss interconnect structure for use in microelectronic circuitsINTEL CORP·Filed 2005·Granted Apr 1, 2008·5 cites·18 claims
- 1573US8015429B2Clock and data recovery (CDR) method and apparatusINTEL CORP·Filed 2008·Granted Sep 6, 2011·4 cites·20 claims
- 1673US6522186B2Hierarchical clock grid for on-die salphasic clockingINTEL CORP·Filed 2001·Granted Feb 18, 2003·18 cites·27 claims
- 1772US11791331B2Integrated circuit structures including backside viasINTEL CORP·Filed 2021·Granted Oct 17, 2023·0 cites·16 claims
- 1863US8571513B2Integrated circuit passive signal distributionO'MAHONY FRANK·Filed 2012·Granted Oct 29, 2013·1 cites·20 claims
- 1959US9564430B2Macro-transistor devicesHYVONEN SAMI·Filed 2011·Granted Feb 7, 2017·1 cites·23 claims
- 2059US2021202472A1Integrated circuit structures including backside viasINTEL CORP·Filed 2019·Application pending·0 cites
- 2158US8213894B2Integrated circuit passive signal distributionO'MAHONY FRANK·Filed 2005·Granted Jul 3, 2012·1 cites·27 claims
- 2257US12184751B2Wide-range inductor-based delay-cell and area efficient termination switch controlINTEL CORP·Filed 2021·Granted Dec 31, 2024·0 cites·21 claims
- 2357US7650271B2Time-domain device noise simulatorINTEL CORP·Filed 2006·Granted Jan 19, 2010·2 cites·14 claims
- 2457US7573326B2Forwarded clock filteringINTEL CORP·Filed 2005·Granted Aug 11, 2009·2 cites·15 claims
- 2555US12265483B2Shunt-series and series-shunt inductively peaked clock buffer, and asymmetric multiplexer and de-multiplexerINTEL CORP·Filed 2021·Granted Apr 1, 2025·0 cites·20 claims
- 2653US9761585B2Macro transistor devicesINTEL CORP·Filed 2017·Granted Sep 12, 2017·0 cites·20 claims
- 2750US8375242B2Clock and data recovery (CDR) method and apparatusINTEL CORP·Filed 2011·Granted Feb 12, 2013·0 cites·20 claims
- 2847US7961039B2Forwarded clock filteringINTEL CORP·Filed 2009·Granted Jun 14, 2011·0 cites·16 claims
- 2940US2007001704A1Method and apparatus for equalization of connection padsO'MAHONY FRANK·Filed 2005·Application pending·0 cites
- 3039US2007146011A1Duty cycle adjustmentO'MAHONY FRANK P·Filed 2005·Application pending·0 cites
- 3138US9935063B2Rlink-on-die inductor structures to improve signalingINTEL CORP·Filed 2016·Granted Apr 3, 2018·0 cites·20 claims
- 3234US2009322389A1Jitter attenuating delay locked loop (dll) using a regenerative delay lineSINGH GUNEET·Filed 2008·Application pending·0 cites
- 3333US2009243672A1Multi-pole delay element delay locked loop (dll)SINGH GUNEET·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →