Inventor · disambiguated record
Buck Gremel
Also filed as: GREMEL BUCK · GREMEL BUCK W
9 granted patents·3 pending applications·120 citations·filing 1996–2021
86Inventor score
Top patents by PatentIndex Score
12 records- 0194US7152128B2General input/output architecture, protocol and related methods to manage data integrityINTEL CORP·Filed 2002·Granted Dec 19, 2006·85 cites·31 claims
- 0291US7353313B2General input/output architecture, protocol and related methods to manage data integrityINTEL CORP·Filed 2006·Granted Apr 1, 2008·15 cites·24 claims
- 0372US8935578B2Method and apparatus for optimizing power and latency on a linkINTEL CORP·Filed 2012·Granted Jan 13, 2015·2 cites·30 claims
- 0467US11841752B2Controlling average power limits of a processorINTEL CORP·Filed 2021·Granted Dec 12, 2023·0 cites·21 claims
- 0560US11079819B2Controlling average power limits of a processorINTEL CORP·Filed 2018·Granted Aug 3, 2021·0 cites·20 claims
- 0657US7257659B2Method for signaling PCI/PCI-X standard hot-plug controller (SHPC) command statusINTEL CORP·Filed 2003·Granted Aug 14, 2007·6 cites·30 claims
- 0752US9336175B2Utilization-aware low-overhead link-width modulation for power reduction in interconnectsINTEL CORP·Filed 2015·Granted May 10, 2016·0 cites·25 claims
- 0851US9053244B2Utilization-aware low-overhead link-width modulation for power reduction in interconnectsVARMA ANKUSH·Filed 2012·Granted Jun 9, 2015·0 cites·24 claims
- 0949US2016147280A1Controlling average power limits of a processorTHOMAS TESSIL·Filed 2014·Application pending·0 cites
- 1044US2005144339A1Speculative processing of transaction layer packetsFiled 2003·Application pending·0 cites
- 1142US2003115513A1Error forwarding in an enhanced general input/output architecture and related methodsFiled 2001·Application pending·0 cites
- 1232US5912832AFast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded addersUNIV TEXAS·Filed 1996·Granted Jun 15, 1999·12 cites·10 claims
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