Inventor · disambiguated record
Ren-Song Tsay
Also filed as: TSAY REN-SONG
12 granted patents·6 pending applications·598 citations·filing 1993–2014
91Inventor score
Top patents by PatentIndex Score
18 records- 0193US6009256ASimulation/emulation system and methodAXIS SYSTEMS INC·Filed 1997·Granted Dec 28, 1999·261 cites·45 claims
- 0290US6134516ASimulation server system and methodAXIS SYSTEMS INC·Filed 1998·Granted Oct 17, 2000·196 cites·27 claims
- 0381US5461576AElectronic design automation tool for the design of a semiconductor integrated circuit chipARCSYS INC·Filed 1993·Granted Oct 24, 1995·124 cites·7 claims
- 0474US8407647B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioCHANG FONG-YUAN·Filed 2010·Granted Mar 26, 2013·3 cites·12 claims
- 0572US8875081B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioSYNOPSYS TAIWAN CO LTD·Filed 2013·Granted Oct 28, 2014·2 cites·10 claims
- 0666US8423343B2High-parallelism synchronization approach for multi-core instruction-set simulationWU MENG-HUAN·Filed 2011·Granted Apr 16, 2013·3 cites·10 claims
- 0765US8336001B2Method for improving yield rate using redundant wire insertionCHANG FONG-YUAN·Filed 2010·Granted Dec 18, 2012·2 cites·12 claims
- 0864US10192019B2Separation and minimum wire length constrained maze routing method and systemSYNOPSYS INC·Filed 2014·Granted Jan 29, 2019·1 cites·17 claims
- 0963US8352924B2Method and device for multi-core instruction-set simulationNAT UNIV TSING HUA·Filed 2009·Granted Jan 8, 2013·4 cites·13 claims
- 1061US8549468B2Method, system and computer readable storage device for generating software transaction-level modeling (TLM) modelWU MENG-HUAN·Filed 2010·Granted Oct 1, 2013·2 cites·14 claims
- 1158US9665679B2Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratiosSYNOPSYS INC·Filed 2014·Granted May 30, 2017·0 cites·14 claims
- 1245US9195788B2Resource-oriented method of power analysis for embedded systemNAT UNIV TSING HUA·Filed 2013·Granted Nov 24, 2015·0 cites·7 claims
- 1339US2013179864A1Deadlock free synchronization synthesizer for must-happen-before relations in parallel programs and method thereofLu yi-shan·Filed 2012·Application pending·0 cites
- 1435US2012233410A1Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core SimulationFU CHENG-YANG·Filed 2011·Application pending·0 cites
- 1533US2012197625A1Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive SchedulingWANG PENG-CHIH·Filed 2011·Application pending·0 cites
- 1633US2011218791A1System for Simulating Processor Power Consumption and Method of the SameLEE CHIEN-MIN·Filed 2010·Application pending·0 cites
- 1732US2012185231A1Cycle-Count-Accurate (CCA) Processor Modeling for System-Level SimulationLO CHEN-KANG·Filed 2011·Application pending·0 cites
- 1831US2013054854A1Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention AnalysisLi mao-lin·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →