Inventor · disambiguated record
Remi Coquand
Also filed as: COQUAND REMI · COQUAND RÉMI
23 granted patents·6 pending applications·58 citations·filing 2017–2025
93Inventor score
Top patents by PatentIndex Score
29 records- 0194US11081547B2Method for making superimposed transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Aug 3, 2021·8 cites·15 claims
- 0294US10263077B1Method of fabricating a FET transistor having a strained channelCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Apr 16, 2019·12 cites·12 claims
- 0390US10217849B2Method for making a semiconductor device with nanowire and aligned external and internal spacersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Feb 26, 2019·7 cites·14 claims
- 0488US10269930B2Method for producing a semiconductor device with self-aligned internal spacersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Apr 23, 2019·6 cites·15 claims
- 0588US10134875B2Method for fabricating a transistor having a vertical channel having nano layersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Nov 20, 2018·5 cites·15 claims
- 0687US10896956B2Field effect transistor with reduced contact resistanceCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Jan 19, 2021·5 cites·13 claims
- 0783US10714392B2Optimizing junctions of gate all around structures with channel pull backIBM·Filed 2018·Granted Jul 14, 2020·3 cites·15 claims
- 0882US10217842B2Method for making a semiconductor device with self-aligned inner spacersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Feb 26, 2019·3 cites·13 claims
- 0980US10431683B2Method for making a semiconductor device with a compressive stressed channelCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Oct 1, 2019·3 cites·18 claims
- 1076US10141424B2Method of producing a channel structure formed from a plurality of strained semiconductor barsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Nov 27, 2018·2 cites·10 claims
- 1176US10109735B2Process for fabricating a field effect transistor having a coating gateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Oct 23, 2018·2 cites·12 claims
- 1271US10818775B2Method for fabricating a field-effect transistorCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Oct 27, 2020·1 cites·13 claims
- 1371US2025321493A1Method for manufacturing a micro-nanometric hierarchical structure and micro-nanometric hierarchical structure obtained by such a methodST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1470US10553723B2Method for forming doped extension regions in a structure having superimposed nanowiresCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Feb 4, 2020·1 cites·8 claims
- 1569US11515392B2Semiconductor divice having a carbon containing insulation layer formed under the source/drainCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2021·Granted Nov 29, 2022·0 cites·13 claims
- 1667US11450755B2Electronic device including at least one nano-objectCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2020·Granted Sep 20, 2022·0 cites·20 claims
- 1762US11575003B2Creation of stress in the channel of a nanosheet transistorIBM·Filed 2021·Granted Feb 7, 2023·0 cites·6 claims
- 1860US11088247B2Method of fabrication of a semiconductor device including one or more nanostructuresCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2020·Granted Aug 10, 2021·0 cites·15 claims
- 1958US2024215263A1Memory device comprising large contact surfaces between the conduction channel and the contact regionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Application pending·0 cites
- 2058US2024213359A1Microelectronic device comprising large contact surfaces between the conduction channel and the source and drain regionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Application pending·0 cites
- 2158US2024234573A1Microelectronic fet device including large contact surfaces between the conduction channel and the source and drain regionsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2023·Application pending·0 cites
- 2257US11049933B2Creation of stress in the channel of a nanosheet transistorIBM·Filed 2019·Granted Jun 29, 2021·0 cites·11 claims
- 2352US10727320B2Method of manufacturing at least one field effect transistor having epitaxially grown electrodesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Jul 28, 2020·0 cites·18 claims
- 2451US2019198614A1Method of fabrication of a semiconductor device including one or more nanostructuresCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Application pending·0 cites
- 2548US11177371B2Transistor with superposed bars and double-gate structureCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Nov 16, 2021·0 cites·13 claims
- 2645US2020111872A1Structure with superimposed semiconductor bars having a uniform semiconductor casingCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Application pending·0 cites
- 2744US10256102B2Method for fabricating a field effect transistor having a surrounding gridCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2018·Granted Apr 9, 2019·0 cites·13 claims
- 2841US10096694B2Process for fabricating a vertical-channel nanolayer transistorCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Oct 9, 2018·0 cites·18 claims
- 2939US10147788B2Process for fabricating a field effect transistor having a coating gateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2017·Granted Dec 4, 2018·0 cites·14 claims
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