Inventor · disambiguated record
Robert Louis Hodges
Also filed as: HODGES ROBERT · HODGES ROBERT L · HODGES ROBERT LOUIS
33 granted patents·1 pending application·520 citations·filing 1991–2006
98Inventor score
Top patents by PatentIndex Score
34 records- 0186US5260229AMethod of forming isolated regions of oxideSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Nov 9, 1993·86 cites·13 claims
- 0281US5831897ASRAM memory cell design having complementary dual pass gatesST MICROELECTRONICS INC·Filed 1996·Granted Nov 3, 1998·47 cites·14 claims
- 0380US5742095AMethod of fabricating planar regions in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Apr 21, 1998·50 cites·8 claims
- 0471US5439846ASelf-aligned method for forming contact with zero offset to gateSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 8, 1995·40 cites·27 claims
- 0570US7598146B2Self-aligned gate and methodST MICROELECTRONICS INC·Filed 2006·Granted Oct 6, 2009·2 cites·20 claims
- 0664US5811865ADielectric in an integrated circuitST MICROELECTRONICS INC·Filed 1996·Granted Sep 22, 1998·28 cites·9 claims
- 0764US5541455AMethod of forming low resistance contacts at the junction between regions having different conductivity typesSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jul 30, 1996·20 cites·8 claims
- 0863US5432129AMethod of forming low resistance contacts at the junction between regions having different conductivity typesSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Jul 11, 1995·19 cites·23 claims
- 0960US6514811B2Method for memory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 2001·Granted Feb 4, 2003·6 cites·13 claims
- 1058US5192707AMethod of forming isolated regions of oxideSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Mar 9, 1993·26 cites·18 claims
- 1155US7126190B2Self-aligned gate and methodST MICROELECTRONICS INC·Filed 2004·Granted Oct 24, 2006·3 cites·19 claims
- 1255US5682052AMethod for forming isolated intra-polycrystalline silicon structureSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Oct 28, 1997·18 cites·7 claims
- 1354US6774001B2Self-aligned gate and methodST MICROELECTRONICS INC·Filed 2000·Granted Aug 10, 2004·3 cites·12 claims
- 1452US6661064B2Memory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 2002·Granted Dec 9, 2003·3 cites·5 claims
- 1552US6022788AMethod of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed therebyST MICROELECTRONICS INC·Filed 1997·Granted Feb 8, 2000·18 cites·33 claims
- 1651US5344790AMaking integrated circuit transistor having drain junction offsetSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Sep 6, 1994·11 cites·9 claims
- 1750US5927992AMethod of forming a dielectric in an integrated circuitST MICROELECTRONICS INC·Filed 1994·Granted Jul 27, 1999·18 cites·21 claims
- 1849US5543343AMethod fabricating an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 6, 1996·16 cites·28 claims
- 1948US6087709AMethod of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed therebyST MICROELECTRONICS INC·Filed 1999·Granted Jul 11, 2000·14 cites·7 claims
- 2048US6051864AMemory masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 1997·Granted Apr 18, 2000·10 cites·15 claims
- 2146US6011711ASRAM cell with p-channel pull-up sources connected to bit linesST MICROELECTRONICS INC·Filed 1996·Granted Jan 4, 2000·10 cites·22 claims
- 2245US5338968AMethod of forming isolated regions of oxideSGS THOMSON·Filed 1992·Granted Aug 16, 1994·16 cites·3 claims
- 2344US5793114ASelf-aligned method for forming contact with zero offset to gateSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Aug 11, 1998·10 cites·32 claims
- 2443US5460983AMethod for forming isolated intra-polycrystalline silicon structuresSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Oct 24, 1995·11 cites·6 claims
- 2542US5286672AMethod for forming field oxide regionsSGS THOMSON MICROELECTRONICS·Filed 1992·Granted Feb 15, 1994·11 cites·4 claims
- 2640US6040233AMethod of making a shallow trench isolation with thin nitride as gate dielectricST MICROELECTRONICS INC·Filed 1999·Granted Mar 21, 2000·5 cites·16 claims
- 2739US6284584B1Method of masking for periphery salicidation of active regionsST MICROELECTRONICS INC·Filed 1997·Granted Sep 4, 2001·5 cites·6 claims
- 2839US6107194AMethod of fabricating an integrated circuitST MICROELECTRONICS INC·Filed 1997·Granted Aug 22, 2000·5 cites·24 claims
- 2936US2003136999A1Semiconductor device with deposited oxideFiled 2002·Application pending·0 cites
- 3034US5506440APoly-buffered LOCOS processSGS THOMSON MICROELECTRONICS·Filed 1994·Granted Apr 9, 1996·5 cites·5 claims
- 3133US5952707AShallow trench isolation with thin nitride as gate dielectricST MICROELECTRONICS INC·Filed 1997·Granted Sep 14, 1999·2 cites·16 claims
- 3232US5977607AMethod of forming isolated regions of oxideST MICROELECTRONICS INC·Filed 1995·Granted Nov 2, 1999·2 cites·1 claims
- 3331US5729036AIntegrated circuit transistor having drain junction offsetSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Mar 17, 1998·0 cites·20 claims
- 3430US5420453AIntermediate structure for forming isolated regions of oxideSGS THOMSON MICROELECTRONICS·Filed 1994·Granted May 30, 1995·0 cites·5 claims
Join the waitlist — get patent alerts
Get an alert when Robert Louis Hodges files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →