Inventor · disambiguated record
Anshuman Chandra
Also filed as: CHANDRA ANSHUMAN
7 granted patents·2 pending applications·38 citations·filing 2009–2024
79Inventor score
Top patents by PatentIndex Score
9 records- 0190US12066490B2Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosisTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 20, 2024·1 cites·20 claims
- 0287US8065651B2Implementing hierarchical design-for-test logic for modular circuit designKAPUR ROHIT·Filed 2009·Granted Nov 22, 2011·24 cites·21 claims
- 0386US8479067B2Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitryCHANDRA ANSHUMAN·Filed 2010·Granted Jul 2, 2013·12 cites·25 claims
- 0480US2024361385A1Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and DiagnosisTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0561US9239897B2Hierarchical testing architecture using core circuit with pseudo-interfacesSYNOPSYS INC·Filed 2014·Granted Jan 19, 2016·1 cites·19 claims
- 0653US9417287B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2014·Granted Aug 16, 2016·0 cites·20 claims
- 0753US2016341795A1Scheme for Masking Output of Scan Chains in Test CircuitSYNOPSYS INC·Filed 2016·Application pending·0 cites
- 0848US10067187B2Handling of undesirable distribution of unknown values in testing of circuit using automated test equipmentSYNOPSYS INC·Filed 2014·Granted Sep 4, 2018·0 cites·19 claims
- 0947US10621298B2Automatically generated schematics and visualizationSYNOPSYS INC·Filed 2016·Granted Apr 14, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →