Inventor · disambiguated record
Hans-Werner Tast
Also filed as: TAST HANS-WERNER
41 granted patents·1 pending application·656 citations·filing 1992–2016
97Inventor score
Top patents by PatentIndex Score
42 records- 0195US5761734AToken-based serialisation of instructions in a multiprocessor systemIBM·Filed 1996·Granted Jun 2, 1998·272 cites·24 claims
- 0293US9665486B2Hierarchical cache structure and handling thereofIBM·Filed 2016·Granted May 30, 2017·10 cites·20 claims
- 0393US9563568B2Hierarchical cache structure and handling thereofIBM·Filed 2015·Granted Feb 7, 2017·9 cites·20 claims
- 0493US9274959B2Handling virtual memory address synonyms in a multi-level cache hierarchy structureGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 1, 2016·23 cites·20 claims
- 0592US8041894B2Method and system for a multi-level virtual/real cache system with synonym resolutionIBM·Filed 2008·Granted Oct 18, 2011·30 cites·15 claims
- 0690US9183146B2Hierarchical cache structure and handling thereofIBM·Filed 2013·Granted Nov 10, 2015·11 cites·20 claims
- 0782US6968476B2Checkpointing a superscalar, out-of-order processor for error recoveryIBM·Filed 2002·Granted Nov 22, 2005·33 cites·13 claims
- 0878US7987384B2Method, system, and computer program product for handling errors in a cache without processor core recoveryIBM·Filed 2008·Granted Jul 26, 2011·9 cites·30 claims
- 0978US7783690B2Electronic circuit for implementing a permutation operationIBM·Filed 2006·Granted Aug 24, 2010·12 cites·15 claims
- 1077US9384131B2Systems and methods for accessing cache memoryIBM·Filed 2013·Granted Jul 5, 2016·4 cites·19 claims
- 1176US9886395B2Evicting cached storesIBM·Filed 2015·Granted Feb 6, 2018·2 cites·7 claims
- 1276US9323673B2Hierarchical cache structure and handling thereofIBM·Filed 2013·Granted Apr 26, 2016·3 cites·20 claims
- 1374US8108197B2Method to verify an implemented coherency algorithm of a multi processor environmentHABERMANN CHRISTIAN·Filed 2008·Granted Jan 31, 2012·7 cites·15 claims
- 1474US5974543AApparatus and method for performing subroutine call and return operationsIBM·Filed 1998·Granted Oct 26, 1999·79 cites·29 claims
- 1570US9658967B2Evicting cached storesIBM·Filed 2014·Granted May 23, 2017·2 cites·7 claims
- 1670US8302043B2Verification of logic circuit designs using dynamic clock gatingHABERMANN CHRISTIAN·Filed 2010·Granted Oct 30, 2012·3 cites·15 claims
- 1770US7380065B2Performance of a cache by detecting cache lines that have been reusedIBM·Filed 2005·Granted May 27, 2008·5 cites·8 claims
- 1869US8977823B2Store buffer for transactional memoryIBM·Filed 2012·Granted Mar 10, 2015·2 cites·22 claims
- 1965US5872944ABus with request-dependent matching of the bandwidth available in both directionsIBM·Filed 1996·Granted Feb 16, 1999·48 cites·10 claims
- 2064US9298631B2Managing transactional and non-transactional store observabilityALEXANDER KHARY J·Filed 2012·Granted Mar 29, 2016·1 cites·18 claims
- 2158US6681313B1Method and system for fast access to a translation lookaside bufferIBM·Filed 2000·Granted Jan 20, 2004·9 cites·10 claims
- 2257US9588894B2Store cache for transactional memoryIBM·Filed 2014·Granted Mar 7, 2017·0 cites·10 claims
- 2357US7552286B2Performance of a cache by detecting cache lines that have been reusedIBM·Filed 2008·Granted Jun 23, 2009·1 cites·8 claims
- 2456US9588893B2Store cache for transactional memoryIBM·Filed 2014·Granted Mar 7, 2017·0 cites·10 claims
- 2556US8001411B2Generating a local clock domain using dynamic controlsIBM·Filed 2007·Granted Aug 16, 2011·3 cites·20 claims
- 2654US8082399B2Cache bounded reference countingPASCH EBERHARD·Filed 2008·Granted Dec 20, 2011·4 cites·1 claims
- 2753US9378143B2Managing transactional and non-transactional store observabilityIBM·Filed 2013·Granted Jun 28, 2016·0 cites·9 claims
- 2852US6108771ARegister renaming with a pool of physical registersIBM·Filed 1998·Granted Aug 22, 2000·26 cites·7 claims
- 2951US8015451B2Controlling an unreliable data transfer in a data channelIBM·Filed 2009·Granted Sep 6, 2011·0 cites·18 claims
- 3051US5311519AMultiplexerIBM·Filed 1992·Granted May 10, 1994·15 cites·12 claims
- 3150US8856444B2Data caching methodHABERMANN CHRISTIAN·Filed 2012·Granted Oct 7, 2014·0 cites·6 claims
- 3248US9075732B2Data caching methodHABERMANN CHRISTIAN·Filed 2011·Granted Jul 7, 2015·0 cites·12 claims
- 3346US8891279B2Enhanced wiring structure for a cache supporting auxiliary data outputHABERMANN CHRISTIAN·Filed 2012·Granted Nov 18, 2014·0 cites·20 claims
- 3445US8495452B2Handling corrupted background data in an out of order execution environmentFEE MICHAEL·Filed 2011·Granted Jul 23, 2013·0 cites·21 claims
- 3544US8516200B2Avoiding cross-interrogates in a streaming data optimized L1 cacheHABERMANN CHRISTIAN·Filed 2010·Granted Aug 20, 2013·0 cites·20 claims
- 3643US7469332B2Systems and methods for adaptively mapping an instruction cacheIBM·Filed 2005·Granted Dec 23, 2008·0 cites·14 claims
- 3742US5870601AData processing apparatus and method for correcting faulty microcode in a ROM device via a flag microinstruction in a RAM device including corrected microcodeIBM·Filed 1995·Granted Feb 9, 1999·18 cites·8 claims
- 3841US6353548B2Method and data processing system for data lookupsIBM·Filed 2000·Granted Mar 5, 2002·3 cites·15 claims
- 3940US2002152259A1Pre-committing instruction sequencesIBM·Filed 2002·Application pending·0 cites
- 4036US5634047AMethod for executing branch instructions by processing loop end conditions in a second processorIBM·Filed 1996·Granted May 27, 1997·11 cites·15 claims
- 4134US6518793B2Embedding of dynamic circuits in a static environmentIBM·Filed 2001·Granted Feb 11, 2003·0 cites·19 claims
- 4228US6032233AStorage array allowing for multiple, simultaneous write accessesIBM·Filed 1997·Granted Feb 29, 2000·1 cites·25 claims
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