Inventor · disambiguated record
Uwe Kranich
Also filed as: KRANICH UWE
18 granted patents·1 pending application·989 citations·filing 1992–2022
96Inventor score
Files withADVANCED MICRO DEVICES INC14HOME BOX OFFICE INC2ADVANCE MICRO DEVICES INC1ADVANCED MICRO SYSTEMS INC1GLOBALFOUNDRIES INC1
Top patents by PatentIndex Score
19 records- 0197US7012604B1System architecture for high speed ray tracingADVANCED MICRO DEVICES INC·Filed 2002·Granted Mar 14, 2006·144 cites·23 claims
- 0296US6651163B1Exception handling with reduced overhead in a multithreaded multiprocessing systemADVANCED MICRO DEVICES INC·Filed 2000·Granted Nov 18, 2003·147 cites·14 claims
- 0389US6574725B1Method and mechanism for speculatively executing threads of instructionsADVANCED MICRO DEVICES INC·Filed 1999·Granted Jun 3, 2003·145 cites·29 claims
- 0485US6185675B1Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocksADVANCED MICRO DEVICES INC·Filed 1998·Granted Feb 6, 2001·121 cites·27 claims
- 0580US6157996AProcessor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register spaceADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 5, 2000·95 cites·22 claims
- 0676US6456891B1System and method for transparent handling of extended register statesADVANCED MICRO DEVICES INC·Filed 1999·Granted Sep 24, 2002·71 cites·43 claims
- 0775US11252333B2Production shot design systemHOME BOX OFFICE INC·Filed 2019·Granted Feb 15, 2022·2 cites·20 claims
- 0869US6230259B1Transparent extended state saveADVANCED MICRO DEVICES INC·Filed 1997·Granted May 8, 2001·55 cites·38 claims
- 0966US5900022AApparatus and method for reducing the cache miss penalty in a virtual addressed memory system by using a speculative address generator and an accurate address generatorADVANCED MICRO DEVICES INC·Filed 1997·Granted May 4, 1999·51 cites·34 claims
- 1065US5850534AMethod and apparatus for reducing cache snooping overhead in a multilevel cache systemADVANCED MICRO DEVICES INC·Filed 1995·Granted Dec 15, 1998·48 cites·10 claims
- 1165US5524225ACache system and method for providing software controlled writebackADVANCED MICRO DEVICES INC·Filed 1992·Granted Jun 4, 1996·44 cites·10 claims
- 1262US7890740B2Processor comprising a first and a second mode of operation and method of operating the sameGLOBALFOUNDRIES INC·Filed 2007·Granted Feb 15, 2011·2 cites·20 claims
- 1362US7689809B2Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating systemADVANCED MICRO DEVICES INC·Filed 2008·Granted Mar 30, 2010·2 cites·22 claims
- 1458US11785332B2Production shot design systemHOME BOX OFFICE INC·Filed 2022·Granted Oct 10, 2023·0 cites·20 claims
- 1551US5761443AComputer system employing a bus conversion bridge for interfacing a master device residing on a multiplexed peripheral bus to a slave device residing on a split-address, split-data multiplexed peripheral busADVANCED MICRO SYSTEMS INC·Filed 1995·Granted Jun 2, 1998·28 cites·9 claims
- 1645US5761709AWrite cache for servicing write requests within a predetermined address rangeADVANCED MICRO DEVICES INC·Filed 1995·Granted Jun 2, 1998·18 cites·4 claims
- 1742US2006095593A1Parallel processing mechanism for multi-processor systemsADVANCED MICRO DEVICES INC·Filed 2005·Application pending·0 cites
- 1840US5752263AApparatus and method for reducing read miss latency by predicting sequential instruction read-aheadsADVANCED MICRO DEVICES INC·Filed 1995·Granted May 12, 1998·13 cites·19 claims
- 1931US5546560ADevice and method for reducing bus activity in a computer system having multiple bus-mastersADVANCE MICRO DEVICES INC·Filed 1993·Granted Aug 13, 1996·3 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →