Inventor · disambiguated record
Richard P. Kelly
Also filed as: KELLY RICHARD P
19 granted patents·429 citations·filing 1973–1990
95Inventor score
Technology areasG06F
Files withHONEYWELL INF SYSTEMS9BULL HN INFORMATION SYST8BULL NH INFORMATION SYSTEMS IN1HONEYWELL BULL1
Top patents by PatentIndex Score
19 records- 0189US3938096AApparatus for developing an address of a segment within main memory and an absolute address of an operand within the segmentHONEYWELL INF SYSTEMS·Filed 1973·Granted Feb 10, 1976·70 cites·8 claims
- 0283US5193181ARecovery method and apparatus for a pipelined processing unit of a multiprocessor systemBULL HN INFORMATION SYST·Filed 1990·Granted Mar 9, 1993·102 cites·18 claims
- 0375US4254462AHardware/firmware communication line adapterHONEYWELL INF SYSTEMS·Filed 1978·Granted Mar 3, 1981·35 cites·4 claims
- 0466US4458308AMicroprocessor controlled communications controller having a stretched clock cycleHONEYWELL INF SYSTEMS·Filed 1980·Granted Jul 3, 1984·31 cites·4 claims
- 0562US4980819AMechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing systemBULL HN INFORMATION SYST·Filed 1988·Granted Dec 25, 1990·30 cites·19 claims
- 0662US4407014ACommunications subsystem having a direct connect clockHONEYWELL INF SYSTEMS·Filed 1980·Granted Sep 27, 1983·27 cites·5 claims
- 0760US4641305AControl store memory read error resiliency method and apparatusHONEYWELL INF SYSTEMS·Filed 1984·Granted Feb 3, 1987·23 cites·14 claims
- 0851US5179671AApparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectivelyBULL HN INFORMATION SYST·Filed 1989·Granted Jan 12, 1993·19 cites·19 claims
- 0950US5123097AApparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategyBULL HN INFORMATION SYST·Filed 1989·Granted Jun 16, 1992·18 cites·17 claims
- 1045US4494186AAutomatic data steering and data formatting mechanismHONEYWELL INF SYSTEMS·Filed 1981·Granted Jan 15, 1985·14 cites·5 claims
- 1143US4942547AMultiprocessors on a single semiconductor chipHONEYWELL BULL·Filed 1987·Granted Jul 17, 1990·12 cites·8 claims
- 1242US4670835ADistributed control store word architectureHONEYWELL INF SYSTEMS·Filed 1984·Granted Jun 2, 1987·11 cites·8 claims
- 1339US4379340ACommunications subsystem idle link state detectorHONEYWELL INF SYSTEMS·Filed 1980·Granted Apr 5, 1983·10 cites·5 claims
- 1437US4418384ACommunication subsystem with an automatic abort transmission upon transmit underrunHONEYWELL INF SYSTEMS·Filed 1980·Granted Nov 29, 1983·8 cites·6 claims
- 1536US5148530AMethod for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bitsBULL HN INFORMATION SYST·Filed 1989·Granted Sep 15, 1992·6 cites·3 claims
- 1634US4901222AMethod and apparatus for backing out of a software instruction after execution has begunBULL NH INFORMATION SYSTEMS IN·Filed 1987·Granted Feb 13, 1990·6 cites·11 claims
- 1730US5197133AControl store addressing from multiple sourcesBULL HN INFORMATION SYST·Filed 1988·Granted Mar 23, 1993·4 cites·8 claims
- 1830US4916601AMeans for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal functionBULL HN INFORMATION SYST·Filed 1988·Granted Apr 10, 1990·1 cites·4 claims
- 1929US5117491ARing reduction logic using parallel determination of ring numbers in a plurality of functional units and forced ring numbers by instruction decodingBULL HN INFORMATION SYST·Filed 1989·Granted May 26, 1992·2 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →