Inventor · disambiguated record
Werner Juchmes
Also filed as: JUCHMES WERNER
9 granted patents·1 pending application·24 citations·filing 2008–2020
82Inventor score
Top patents by PatentIndex Score
10 records- 0187US9431096B1Hierarchical negative bitline boost write assist for SRAM memory devicesIBM·Filed 2015·Granted Aug 30, 2016·10 cites·13 claims
- 0268US8422313B2Reduced power consumption memory circuitryBUETTNER STEFAN·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 0366US7844871B2Test interface for memory elementsIBM·Filed 2008·Granted Nov 30, 2010·6 cites·1 claims
- 0452US11043938B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2019·Granted Jun 22, 2021·0 cites·19 claims
- 0552US7558138B1Bypass circuit for memory arraysIBM·Filed 2008·Granted Jul 7, 2009·4 cites·1 claims
- 0651US10984160B1Analysis and modification of circuit designsIBM·Filed 2020·Granted Apr 20, 2021·0 cites·20 claims
- 0747US10367481B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2018·Granted Jul 30, 2019·0 cites·1 claims
- 0846US10587248B2Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featureIBM·Filed 2017·Granted Mar 10, 2020·0 cites·19 claims
- 0934US9666278B2Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell blockIBM·Filed 2015·Granted May 30, 2017·0 cites·20 claims
- 1031US2013128684A1Reduced leakage banked wordline headerBUETTNER STEFAN·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →