Inventor · disambiguated record
Cheng-Chen Calvin Hsueh
Also filed as: HSUEH CHENG-CHEN · HSUEH CHENG-CHEN CALVIN
19 granted patents·1 pending application·297 citations·filing 1994–2013
95Inventor score
Files withINTEGRATED DEVICE TECH6MACRONIX INT CO LTD6TAIWAN SEMICONDUCTOR MFG4NAT SEMICONDUCTOR CORP1TAIWAN SEMICONDUTOR MFG COMPAN1
Top patents by PatentIndex Score
20 records- 0184US8409997B2Apparatus and method for controlling silicon nitride etching tankWEI ZIN-CHANG·Filed 2007·Granted Apr 2, 2013·11 cites·16 claims
- 0283US5981356AIsolation trenches with protected cornersINTEGRATED DEVICE TECH·Filed 1997·Granted Nov 9, 1999·76 cites·18 claims
- 0382US6444521B1Method to improve nitride floating gate charge trapping for NROM flash memory deviceMACRONIX INT CO LTD·Filed 2000·Granted Sep 3, 2002·38 cites·7 claims
- 0474US6136687AMethod of forming air gaps for reducing interconnect capacitanceINTEGRATED DEVICE TECH·Filed 1997·Granted Oct 24, 2000·51 cites·14 claims
- 0571US8012922B2Wet cleaning solutionTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Sep 6, 2011·1 cites·9 claims
- 0671US7795644B2Integrated circuits with stress memory effect and fabrication methods thereofTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Sep 14, 2010·5 cites·12 claims
- 0769US8012846B2Isolation structures and methods of fabricating isolation structuresTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 6, 2011·4 cites·16 claims
- 0869US5573973AIntegrated circuit having a diamond thin film trench arrangement as a component thereof and methodNAT SEMICONDUCTOR CORP·Filed 1994·Granted Nov 12, 1996·40 cites·18 claims
- 0964US6448136B1Method of manufacturing flash memoryMACRONIX INT CO LTD·Filed 2001·Granted Sep 10, 2002·11 cites·20 claims
- 1063US5859458ASemiconductor device containing a silicon-rich layerINTEGRATED DEVICE TECH·Filed 1996·Granted Jan 12, 1999·18 cites·22 claims
- 1154US6468897B1Method of forming damascene structureMACRONIX INT CO LTD·Filed 2001·Granted Oct 22, 2002·6 cites·20 claims
- 1254US5854503AMaximization of low dielectric constant material between interconnect traces of a semiconductor circuitINTEGRATED DEVICE TECH·Filed 1996·Granted Dec 29, 1998·16 cites·10 claims
- 1352US8834671B2Apparatus and method for controlling silicon nitride etching tankTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 16, 2014·0 cites·12 claims
- 1452US7678694B2Method for fabricating semiconductor device with silicided gateTAIWAN SEMICONDUTOR MFG COMPAN·Filed 2007·Granted Mar 16, 2010·1 cites·23 claims
- 1552US6734064B2Method for fabricating read only memory including forming masking layers with openings and pre-coding the cell and peripheral regionsMACRONIX INT CO LTD·Filed 2003·Granted May 11, 2004·4 cites·8 claims
- 1650US6489213B1Method for manufacturing semiconductor device containing a silicon-rich layerINTEGRATED DEVICE TECH·Filed 1996·Granted Dec 3, 2002·10 cites·26 claims
- 1744US6670247B2Method of fabricating mask read only memoryMACRONIX INT CO LTD·Filed 2001·Granted Dec 30, 2003·2 cites·18 claims
- 1841US6998316B2Method for fabricating read only memory including a first and second exposures to a photoresist layerMACRONIX INT CO LTD·Filed 2004·Granted Feb 14, 2006·1 cites·4 claims
- 1935US2002034867A1Method for manufacturing self-aligned silicide layerFiled 2000·Application pending·0 cites
- 2032US5990009AMaximization of low dielectric constant material between interconnect traces of a semiconductor circuitINTEGRATED DEVICE TECH·Filed 1997·Granted Nov 23, 1999·2 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →