Inventor · disambiguated record
Madhumitra Sharma
Also filed as: SHARMA MADHUMITRA
18 granted patents·4 pending applications·1,552 citations·filing 1997–2001
96Inventor score
Files withCOMPAQ COMPUTER CORP12HEWLETT PACKARD DEVELOPMENT CO3DIGITAL EQUIPMENT CORP2COMPAQ COMPUTERS CORP1
Top patents by PatentIndex Score
22 records- 0191US6055605ATechnique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared cachesCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 25, 2000·181 cites·17 claims
- 0288US6209065B1Mechanism for optimizing generation of commit-signals in a distributed shared-memory systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 27, 2001·144 cites·15 claims
- 0388US6108737AMethod and apparatus for reducing latency of inter-reference ordering in a multiprocessor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 22, 2000·148 cites·21 claims
- 0487US6088771AMechanism for reducing latency of memory barrier operations on a multiprocessor systemDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jul 11, 2000·142 cites·7 claims
- 0586US6014690AEmploying multiple channels for deadlock avoidance in a cache coherency protocolDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jan 11, 2000·128 cites·39 claims
- 0684US6101420AMethod and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directoriesCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 8, 2000·90 cites·21 claims
- 0783US6801986B2Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operationHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 5, 2004·37 cites·24 claims
- 0883US6085276AMulti-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependenciesCOMPAQ COMPUTERS CORP·Filed 1997·Granted Jul 4, 2000·117 cites·20 claims
- 0983US6085263AMethod and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processorCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 4, 2000·111 cites·18 claims
- 1080US6279084B1Shadow commands to optimize sequencing of requests in a switch-based multi-processor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 21, 2001·96 cites·18 claims
- 1176US6154816ALow occupancy protocol for managing concurrent transactions with dependenciesCOMPAQ COMPUTER CORP·Filed 1997·Granted Nov 28, 2000·78 cites·34 claims
- 1275US6094686AMulti-processor system for transferring data without incurring deadlock using hierarchical virtual channelsCOMPAQ COMPUTER CORP·Filed 1998·Granted Jul 25, 2000·73 cites·24 claims
- 1373US6286090B1Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetchesCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 4, 2001·66 cites·10 claims
- 1471US6249520B1High-performance non-blocking switch with multiple channel ordering constraintsCOMPAQ COMPUTER CORP·Filed 1997·Granted Jun 19, 2001·63 cites·46 claims
- 1563US6122714AOrder supporting mechanisms for use in a switch-based multi-processor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Sep 19, 2000·42 cites·26 claims
- 1657US6961825B2Cache coherency mechanism using arbitration masksHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 1, 2005·5 cites·17 claims
- 1755US6202126B1Victimization of clean data blocksCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 13, 2001·30 cites·9 claims
- 1852US6904465B2Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switchHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jun 7, 2005·1 cites·8 claims
- 1942US2002009095A1Multicast decomposition mechanism in a hierarchically order distributed shared memory multiprocessor computer systemFiled 2001·Application pending·0 cites
- 2042US2002146022A1Credit-based flow control technique in a modular multiprocessor systemFiled 2001·Application pending·0 cites
- 2142US2001055277A1Initiate flow control mechanism of a modular multiprocessor systemFiled 2001·Application pending·0 cites
- 2241US2003076831A1Mechanism for packet component merging and channel assignment, and packet decomposition and channel reassignment in a multiprocessor systemFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →