Inventor · disambiguated record
Andre Kowalczyk
Also filed as: KOWALCZYK ANDRE
9 granted patents·302 citations·filing 1993–2006
90Inventor score
Files withSUN MICROSYSTEMS INC3SILICON GRAPHICS INC2TRANSMETA CORP2MASLEID ROBERT PAUL1MIPS TECH INC1
Top patents by PatentIndex Score
9 records- 0192US7142018B2Circuits and methods for detecting and assisting wire transitionsTRANSMETA CORP·Filed 2004·Granted Nov 28, 2006·36 cites·22 claims
- 0289US6622219B2Shared write buffer for use by multiple processor unitsSUN MICROSYSTEMS INC·Filed 2002·Granted Sep 16, 2003·52 cites·11 claims
- 0388US7295041B1Circuits and methods for detecting and assisting wire transitionsTRANSMETA CORP·Filed 2004·Granted Nov 13, 2007·23 cites·20 claims
- 0485US5450607AUnified floating point and integer datapath for a RISC processorMIPS TECH INC·Filed 1993·Granted Sep 12, 1995·134 cites·2 claims
- 0561US7652507B1Circuits and methods for detecting and assisting wire transitionsMASLEID ROBERT PAUL·Filed 2006·Granted Jan 26, 2010·2 cites·25 claims
- 0650US6401175B1Shared write buffer for use by multiple processor unitsSUN MICROSYSTEMS INC·Filed 1999·Granted Jun 4, 2002·20 cites·7 claims
- 0742US5568442ARISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memorySILICON GRAPHICS INC·Filed 1995·Granted Oct 22, 1996·17 cites·2 claims
- 0836US6704822B1Arbitration protocol for a shared data cacheSUN MICROSYSTEMS INC·Filed 1999·Granted Mar 9, 2004·13 cites·62 claims
- 0933US5870574ASystem and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cyclesSILICON GRAPHICS INC·Filed 1996·Granted Feb 9, 1999·5 cites·14 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →