Inventor · disambiguated record
Yeong-Jar Chang
Also filed as: CHANG YEONG-JAR
18 granted patents·5 pending applications·135 citations·filing 2004–2023
93Inventor score
Top patents by PatentIndex Score
23 records- 0191US7506231B2Wrapper testing circuits and method thereof for system-on-a-chipIND TECH RES INST·Filed 2007·Granted Mar 17, 2009·23 cites·8 claims
- 0281US7319625B2Built-in memory current test circuitIND TECH RES INST·Filed 2006·Granted Jan 15, 2008·15 cites·18 claims
- 0380US7716542B2Programmable memory built-in self-test circuit and clock switching circuit thereofFARADAY TECH CORP·Filed 2007·Granted May 11, 2010·14 cites·10 claims
- 0480US7228468B2Method and apparatus of build-in self-diagnosis and repair in a memory with syndrome identificationIND TECH RES INST·Filed 2004·Granted Jun 5, 2007·28 cites·19 claims
- 0573US7912166B2Built-in jitter measurement circuitFARADAY TECH CORP·Filed 2007·Granted Mar 22, 2011·8 cites·17 claims
- 0673US7352212B2Opposite-phase scheme for peak current reductionIND TECH RES INST·Filed 2005·Granted Apr 1, 2008·7 cites·14 claims
- 0771US7603602B2Built-in self test circuit for analog-to-digital converter and phase lock loop and the testing methods thereofFARADAY TECH CORP·Filed 2006·Granted Oct 13, 2009·6 cites·15 claims
- 0870US7495479B1Sample and hold circuit and related data signal detecting method utilizing sample and hold circuitFARADAY TECH CORP·Filed 2007·Granted Feb 24, 2009·8 cites·14 claims
- 0966US7904874B2Opposite-phase scheme for peak current reductionIND TECH RES INST·Filed 2008·Granted Mar 8, 2011·4 cites·6 claims
- 1063US7564285B2Controllable delay line and regulation compensation circuit thereofFARADAY TECH CORP·Filed 2007·Granted Jul 21, 2009·4 cites·8 claims
- 1161US9773080B2Thermal simulation device and methodIND TECH RES INST·Filed 2015·Granted Sep 26, 2017·1 cites·24 claims
- 1259US7475367B2Memory power models related to access information and methods thereofIND TECH RES INST·Filed 2005·Granted Jan 6, 2009·4 cites·9 claims
- 1357US7945404B2Clock jitter measurement circuit and integrated circuit having the sameFARADAY TECH CORP·Filed 2008·Granted May 17, 2011·4 cites·19 claims
- 1456US8404501B2Semiconductor package structure and manufacturing method thereofHUANG PO-YAO·Filed 2010·Granted Mar 26, 2013·2 cites·34 claims
- 1552US2024211787A1Electronic device and method for performing monte carlo analysis based on quantum circuitIND TECH RES INST·Filed 2023·Application pending·0 cites
- 1646US6937106B2Built-in jitter measurement circuit for voltage controlled oscillator and phase locked loopIND TECH RES INST·Filed 2004·Granted Aug 30, 2005·3 cites·6 claims
- 1744US6950046B2IC with built-in self-test and design method thereofIND TECH RES INST·Filed 2004·Granted Sep 27, 2005·4 cites·17 claims
- 1843US2010031206A1Method and technique for analogue circuit synthesisFARADAY TECH CORP·Filed 2009·Application pending·0 cites
- 1939US2006156104A1Wrapper testing circuits and method thereof for system-on-a-chipIND TECH RES INST·Filed 2005·Application pending·0 cites
- 2038US2020134116A1Simulation system and methodIND TECH RES INST·Filed 2018·Application pending·0 cites
- 2135US10628627B2Thermal estimation device and thermal estimation methodCHANG YEONG JAR·Filed 2017·Granted Apr 21, 2020·0 cites·22 claims
- 2235US2010257415A1Instruction-based programmable memory built-in self test circuit and address generator thereofFARADAY TECH CORP·Filed 2009·Application pending·0 cites
- 2334US10009017B2On-chip apparatus and method for jitter measurementFARADAY TECH CORP·Filed 2015·Granted Jun 26, 2018·0 cites·24 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →