Inventor · disambiguated record
Tien-Yueh Liu
Also filed as: LIU TIEN-YUEH
8 granted patents·3 pending applications·46 citations·filing 2002–2017
85Inventor score
Top patents by PatentIndex Score
11 records- 0189US7821038B2Power and ground routing of integrated circuit devices with improved IR drop and chip performanceMEDIATEK INC·Filed 2008·Granted Oct 26, 2010·18 cites·6 claims
- 0280US9698102B2Power and ground routing of integrated circuit devices with improved IR drop and chip performanceMEDIATEK INC·Filed 2016·Granted Jul 4, 2017·3 cites·18 claims
- 0378US8661388B2Method of packing-based macro placement and semiconductor chip using the sameCHEN TUNG-CHIEH·Filed 2009·Granted Feb 25, 2014·10 cites·13 claims
- 0473US8120067B1Power and ground routing of integrated circuit devices with improved IR drop and chip performanceKO CHING-CHUNG·Filed 2011·Granted Feb 21, 2012·3 cites·9 claims
- 0572US8072004B2Power and ground routing of integrated circuit devices with improved IR drop and chip performanceKO CHING-CHUNG·Filed 2010·Granted Dec 6, 2011·3 cites·11 claims
- 0668US9379059B2Power and ground routing of integrated circuit devices with improved IR drop and chip performanceKO CHING-CHUNG·Filed 2011·Granted Jun 28, 2016·2 cites·6 claims
- 0754US6708312B1Method for multi-threshold voltage CMOS process optimizationSILICON INTEGRATED SYS CORP·Filed 2002·Granted Mar 16, 2004·7 cites·20 claims
- 0853US10002833B2Power and ground routing of integrated circuit devices with improved IR drop and chip performanceMEDIATEK INC·Filed 2017·Granted Jun 19, 2018·0 cites·20 claims
- 0946US2007157146A1Method of packing-based macro placement and semiconductor chip using the sameMEDIATEK INC·Filed 2006·Application pending·0 cites
- 1042US2008023792A1Filler capacitor with a multiple cell heightMEDIATEK INC·Filed 2006·Application pending·0 cites
- 1141US2008017979A1Semiconductor structure having extra power/ground source connections and layout method thereofCHANG CHIA-YUAN·Filed 2007·Application pending·0 cites
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