Inventor · disambiguated record
Jeffrey H. Oppold
Also filed as: OPPOLD JEFFERY H · OPPOLD JEFFREY H
8 granted patents·2 pending applications·59 citations·filing 1998–2009
85Inventor score
Top patents by PatentIndex Score
10 records- 0186US7716616B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2007·Granted May 11, 2010·12 cites·25 claims
- 0281US7401307B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2004·Granted Jul 15, 2008·24 cites·9 claims
- 0375US7870525B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2008·Granted Jan 11, 2011·5 cites·20 claims
- 0462US6778449B2Method and design for measuring SRAM array leakage macro (ALM)IBM·Filed 2002·Granted Aug 17, 2004·12 cites·17 claims
- 0558US7117428B2Redundancy register architecture for soft-error tolerance and methods of making the sameIBM·Filed 2005·Granted Oct 3, 2006·3 cites·5 claims
- 0652US8196088B2Method and structure for screening NFET-to-PFET device performance offsets within a CMOS processOPPOLD JEFFREY H·Filed 2007·Granted Jun 5, 2012·1 cites·10 claims
- 0745US2009140245A1Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS ProcessIBM·Filed 2008·Application pending·0 cites
- 0843US6917221B2Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuitsIBM·Filed 2003·Granted Jul 12, 2005·2 cites·20 claims
- 0943US2010174503A1Monitoring NFET/PFET Skew in Complementary Metal Oxide Semiconductor DevicesIBM·Filed 2009·Application pending·0 cites
- 1029US6420746B1Three device DRAM cell with integrated capacitor and local interconnectIBM·Filed 1998·Granted Jul 16, 2002·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →