Inventor · disambiguated record
Belliappa Kuttanna
Also filed as: KUTTANA BELLIAPPA · KUTTANNA BELLIAPPA · KUTTANNA BELLIAPPA M · KUTTANNA BELLIAPPA MANAVATTIRA
35 granted patents·4 pending applications·670 citations·filing 1996–2021
98Inventor score
Top patents by PatentIndex Score
39 records- 0196US8669990B2Sharing resources between a CPU and GPUSPRANGLE ERIC·Filed 2009·Granted Mar 11, 2014·61 cites·29 claims
- 0284US6389517B1Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filteredSUN MICROSYSTEMS INC·Filed 2000·Granted May 14, 2002·45 cites·11 claims
- 0382US6347360B1Apparatus and method for preventing cache data eviction during an atomic operationSUN MICROSYSTEMS INC·Filed 2000·Granted Feb 12, 2002·39 cites·8 claims
- 0479US9164764B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeINTEL CORP·Filed 2014·Granted Oct 20, 2015·3 cites·20 claims
- 0578US8762692B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeSCHUCHMAN ETHAN·Filed 2007·Granted Jun 24, 2014·9 cites·31 claims
- 0678US7111153B2Early data return indication mechanismINTEL CORP·Filed 2003·Granted Sep 19, 2006·20 cites·7 claims
- 0777US6269427B1Multiple load miss handling in a cache memory systemIBM·Filed 1999·Granted Jul 31, 2001·77 cites·20 claims
- 0875US6029006AData processor with circuit for regulating instruction throughput while powered and method of operationMOTOROLA INC·Filed 1996·Granted Feb 22, 2000·76 cites·1 claims
- 0974US6470435B2Dual state rename recovery using register usageINTEL CORP·Filed 2000·Granted Oct 22, 2002·20 cites·21 claims
- 1070US8289850B2Interconnect bandwidth throttlerHACKING LANCE·Filed 2011·Granted Oct 16, 2012·2 cites·8 claims
- 1169US6073212AReducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tagsSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 6, 2000·55 cites·24 claims
- 1268US8352770B2Method, system and apparatus for low-power storage of processor context informationINTEL CORP·Filed 2009·Granted Jan 8, 2013·3 cites·18 claims
- 1367US8050177B2Interconnect bandwidth throttlerINTEL CORP·Filed 2008·Granted Nov 1, 2011·3 cites·10 claims
- 1464US7451295B2Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queuesINTEL CORP·Filed 2006·Granted Nov 11, 2008·2 cites·11 claims
- 1563US7877619B2Power mode control method and circuitryRACHAKONDA RAMANA·Filed 2007·Granted Jan 25, 2011·3 cites·20 claims
- 1661US6484240B1Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocolsSUN MICROSYSTEMS INC·Filed 1999·Granted Nov 19, 2002·37 cites·22 claims
- 1759US5873123AProcessor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entriesIBM·Filed 1996·Granted Feb 16, 1999·39 cites·17 claims
- 1857US8392728B2Reducing idle leakage power in an ICHACKING LANCE·Filed 2006·Granted Mar 5, 2013·2 cites·4 claims
- 1956US9600283B2Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power modeINTEL CORP·Filed 2015·Granted Mar 21, 2017·0 cites·19 claims
- 2055US12405890B2Method and apparatus for leveraging simultaneous multithreading for bulk compute operationsINTEL CORP·Filed 2021·Granted Sep 2, 2025·0 cites·24 claims
- 2155US5737751ACache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing systemIBM·Filed 1996·Granted Apr 7, 1998·29 cites·8 claims
- 2254US8719612B2Method, system and apparatus for low-power storage of processor context informationINTEL CORP·Filed 2013·Granted May 6, 2014·0 cites·15 claims
- 2354US5909697AReducing cache misses by snarfing writebacks in non-inclusive memory systemsSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 1, 1999·28 cites·29 claims
- 2453US12112171B2Loop support extensionsINTEL CORP·Filed 2020·Granted Oct 8, 2024·0 cites·17 claims
- 2553US2009043965A1Early data return indication mechanismKUTTANNA BELLIAPPA·Filed 2008·Application pending·0 cites
- 2652US7269711B2Methods and apparatus for address generation in processorsINTEL CORP·Filed 2003·Granted Sep 11, 2007·3 cites·41 claims
- 2749US6321303B1Dynamically modifying queued transactions in a cache memory systemIBM·Filed 1999·Granted Nov 20, 2001·22 cites·20 claims
- 2848US10181171B2Sharing resources between a CPU and GPUINTEL CORP·Filed 2013·Granted Jan 15, 2019·0 cites·19 claims
- 2947US11347828B2Methods, apparatus, articles of manufacture to perform accelerated matrix multiplicationINTEL CORP·Filed 2020·Granted May 31, 2022·0 cites·24 claims
- 3046US5974505AMethod and system for reducing power consumption of a non-blocking cache within a data processing systemIBM·Filed 1997·Granted Oct 26, 1999·15 cites·11 claims
- 3145US6286082B1Apparatus and method to prevent overwriting of modified cache entries prior to write backSUN MOCROSYSTEMS INC·Filed 1999·Granted Sep 4, 2001·22 cites·11 claims
- 3245US5787479AMethod and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operationIBM·Filed 1996·Granted Jul 28, 1998·17 cites·11 claims
- 3344US5897654AMethod and system for efficiently fetching from cache during a cache fill operationIBM·Filed 1997·Granted Apr 27, 1999·16 cites·12 claims
- 3441US2005228971A1Buffer virtualizationSAMRA NICHOLAS G·Filed 2004·Application pending·0 cites
- 3540US2014108684A1Interconnect bandwidth throttlerHACKING LANCE·Filed 2012·Application pending·0 cites
- 3639US6526485B1Apparatus and method for bad address handlingSUN MICROSYSTEMS INC·Filed 1999·Granted Feb 25, 2003·11 cites·11 claims
- 3739US2004117677A1Throttle of an integrated deviceFiled 2002·Application pending·0 cites
- 3835US5721867AMethod and apparatus for executing single beat write store instructions during a cache store linefill operationIBM·Filed 1996·Granted Feb 24, 1998·7 cites·11 claims
- 3932US6311254B1Multiple store miss handling in a cache memory memory systemIBM·Filed 1999·Granted Oct 30, 2001·4 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →