Inventor · disambiguated record
Brion Keller
Also filed as: KELLER BRION · KELLER BRION L
18 granted patents·1 pending application·430 citations·filing 1994–2016
95Inventor score
Files withCADENCE DESIGN SYSTEMS INC8IBM8CHAKRAVADHANULA KARISHNA1CHAKRAVADHANULA KRISHNA1CHICKERMANE VIVEK1
Top patents by PatentIndex Score
19 records- 0194US9404969B1Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad diesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Aug 2, 2016·25 cites·18 claims
- 0294US7487420B2System and method for performing logic failure diagnosis using multiple input signature register output streamsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 3, 2009·32 cites·23 claims
- 0393US7693676B1Low power scan test for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 6, 2010·24 cites·31 claims
- 0493US6611933B1Real-time decoder for scan test patternsIBM·Filed 2000·Granted Aug 26, 2003·83 cites·16 claims
- 0592US9864004B1System and method for diagnosing failure locations in electronic circuitsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 9, 2018·8 cites·20 claims
- 0692US7523370B1Channel masking during integrated circuit testingCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Apr 21, 2009·53 cites·42 claims
- 0791US8468404B1Method and system for reducing switching activity during scan-load operationsCHICKERMANE VIVEK·Filed 2010·Granted Jun 18, 2013·28 cites·24 claims
- 0887US8732632B1Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect testCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 20, 2014·17 cites·14 claims
- 0984US6782501B2System for reducing test data volume in the testing of logic productsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Aug 24, 2004·34 cites·18 claims
- 1082US6986090B2Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuitIBM·Filed 2002·Granted Jan 10, 2006·27 cites·21 claims
- 1182US6708305B1Deterministic random LBISTIBM·Filed 2000·Granted Mar 16, 2004·29 cites·20 claims
- 1277US8296703B1Fault modeling for state retention logicCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Oct 23, 2012·9 cites·26 claims
- 1377US7381986B2Arrangement for testing semiconductor chips while incorporated on a semiconductor waferIBM·Filed 2006·Granted Jun 3, 2008·6 cites·8 claims
- 1473US5546408AHierarchical pattern faults for describing logic circuit failure mechanismsIBM·Filed 1994·Granted Aug 13, 1996·34 cites·20 claims
- 1569US8887019B2Method and system for providing efficient on-product clock generation for domains compatible with compressionCHAKRAVADHANULA KARISHNA·Filed 2010·Granted Nov 11, 2014·5 cites·20 claims
- 1663US7435990B2Arrangement for testing semiconductor chips while incorporated on a semiconductor waferIBM·Filed 2003·Granted Oct 14, 2008·7 cites·5 claims
- 1756US6804803B2Method for testing integrated logic circuitsIBM·Filed 2001·Granted Oct 12, 2004·5 cites·25 claims
- 1846US7103816B2Method and system for reducing test data volume in the testing of logic productsCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Sep 5, 2006·4 cites·6 claims
- 1934US2004139377A1Method and apparatus for compact scan testingIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →