Inventor · disambiguated record
Miles Robert Dooley
Also filed as: DOOLEY MILES R · DOOLEY MILES ROBERT
27 granted patents·3 pending applications·45 citations·filing 2005–2025
93Inventor score
Top patents by PatentIndex Score
30 records- 0184US10372618B2Apparatus and method for maintaining address translation data within an address translation cacheADVANCED RISC MACH LTD·Filed 2016·Granted Aug 6, 2019·7 cites·14 claims
- 0281US8156287B2Adaptive data prefetchBOSE PRADIP·Filed 2009·Granted Apr 10, 2012·11 cites·16 claims
- 0380US10528480B2Apparatus and method for efficient utilisation of an address translation cacheADVANCED RISC MACH LTD·Filed 2017·Granted Jan 7, 2020·5 cites·20 claims
- 0479US10769070B2Multiple stride prefetchingADVANCED RISC MACH LTD·Filed 2018·Granted Sep 8, 2020·3 cites·19 claims
- 0576US9378144B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jun 28, 2016·3 cites·8 claims
- 0674US9465744B2Data prefetch ramp implemenation based on memory utilizationIBM·Filed 2014·Granted Oct 11, 2016·3 cites·9 claims
- 0771US11263138B2Correlated addresses and prefetchingADVANCED RISC MACH LTD·Filed 2018·Granted Mar 1, 2022·1 cites·18 claims
- 0871US9384136B2Modification of prefetch depth based on high latency eventIBM·Filed 2013·Granted Jul 5, 2016·2 cites·19 claims
- 0970US11194574B2Merging memory ordering tracking information for issued load instructionsADVANCED RISC MACH LTD·Filed 2019·Granted Dec 7, 2021·2 cites·22 claims
- 1070US9864694B2Tracking the content of a cache using a way tracker having entries with a cache miss indicatorADVANCED RISC MACH LTD·Filed 2015·Granted Jan 9, 2018·2 cites·11 claims
- 1166US10229066B2Queuing memory access requestsADVANCED RISC MACH LTD·Filed 2016·Granted Mar 12, 2019·1 cites·19 claims
- 1265US12423111B1Static instruction caching in a coprocessor architectureTENSTORRENT USA INC·Filed 2024·Granted Sep 23, 2025·0 cites·20 claims
- 1365US10102143B2Eviction control for an address translation cacheADVANCED RISC MACH LTD·Filed 2016·Granted Oct 16, 2018·1 cites·18 claims
- 1461US7603543B2Method, apparatus and program product for enhancing performance of an in-order processor with long stallsIBM·Filed 2005·Granted Oct 13, 2009·2 cites·3 claims
- 1560US12067395B2Pre-staged instruction registers for variable length instruction set machineTENSTORRENT INC·Filed 2023·Granted Aug 20, 2024·0 cites·22 claims
- 1657US11599358B1Pre-staged instruction registers for variable length instruction set machineTENSTORRENT INC·Filed 2021·Granted Mar 7, 2023·0 cites·21 claims
- 1757US9495297B2Cache line crossing load techniques for a caching systemIBM·Filed 2014·Granted Nov 15, 2016·0 cites·11 claims
- 1857US7752354B2Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processorIBM·Filed 2005·Granted Jul 6, 2010·1 cites·19 claims
- 1956US8856453B2Persistent prefetch data stream settingsDALE JASON N·Filed 2012·Granted Oct 7, 2014·1 cites·20 claims
- 2053US9495298B2Cache line crossing load techniquesIBM·Filed 2015·Granted Nov 15, 2016·0 cites·6 claims
- 2152US2025335363A1Transaction and Request Buffers for Cache Miss HandlingTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2251US11543994B2Controlling access requests of request nodesADVANCED RISC MACH LTD·Filed 2020·Granted Jan 3, 2023·0 cites·16 claims
- 2351US10776043B2Storage circuitry request trackingADVANCED RISC MACH LTD·Filed 2018·Granted Sep 15, 2020·0 cites·14 claims
- 2448US12182427B2Controlling data allocation to storage circuitryADVANCED RISC MACH LTD·Filed 2022·Granted Dec 31, 2024·0 cites·12 claims
- 2548US10983916B2Cache storageADVANCED RISC MACH LTD·Filed 2017·Granted Apr 20, 2021·0 cites·19 claims
- 2647US2006179258A1Method for detecting address match in a deeply pipelined processor designIBM·Filed 2005·Application pending·0 cites
- 2747US2025328456A1Window-Based Memory Dependency PredictorTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2843US8549235B2Method for detecting address match in a deeply pipelined processor designDOOLEY MILES ROBERT·Filed 2011·Granted Oct 1, 2013·0 cites·20 claims
- 2937US8862859B2Efficient support of multiple page size segmentsDOOLEY MILES R·Filed 2010·Granted Oct 14, 2014·0 cites·18 claims
- 3036US8949579B2Ineffective prefetch determination and latency optimizationDOOLEY MILES R·Filed 2010·Granted Feb 3, 2015·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →